Datasheet STGAP2HD (STMicroelectronics) - 6

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STGAP2HD Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 15 V, VDD = 5 V unless otherwise specified) Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics
t INA, INB, SD, Input to output Don See Figure 8 50 75 90 ns BRAKE propagation delay ON t INA, INB, SD, Input to output Doff See Figure 8 50 75 90 ns BRAKE propagation delay OFF tr Rise time CL = 4.7 nF, 30 ns tf Fall time See Figure 8 30 ns MT Matching time(1) 20 ns t INA, INB, SD, deglitch Inputs deglitch filter 20 40 ns BRAKE Common-mode transient VCM = 1500 V, CMTI(2) 100 V/ns immunity, |dVISO/dt| see Figure 9
Supply voltage
VH VH_x UVLO turn-on on 8.6 9.1 9.6 V threshold VH VH_x UVLO turn-off off 7.9 8.4 8.9 V threshold VHhyst VH_x UVLO hysteresis 600 750 950 mV IQHU_A VH undervoltage VH = 7 V 1.3 1.8 mA I quiescent supply current QHU_B IQH_A VH_x quiescent supply 1.3 1.8 mA I current QH_B IQHSBY_A Standby VH_x quiescent 400 550 µA I supply current QHSBY_B IGOFF = 0.2 A; SafeClp GOFF active clamp 2 2.3 V VH floating I VDD quiescent supply QDD 1.8 2.4 mA current I Stand-by VDD quiescent QDDSBY Standby mode 40 80 µA supply current
Logic inputs
V INA, INB, SD, Low-level logic threshold il 0.29·VDD 0.33·VDD 0.37·VDD V BRAKE voltage V INA, INB, SD, High-level logic threshold ih 0.62·VDD 0.66·VDD 0.72·VDD V BRAKE voltage I INA, INB, SD, Logic inputs high-level logic_h V BRAKE input bias current logic = 5 V 33 50 70 µA I INA, INB, SD, Logic inputs low-level logic_l V BRAKE input bias current logic = 0 V 1 µA R INA, INB, SD, Logic inputs pull-down pd 70 100 150 kΩ BRAKE resistor
Interlocking
Interlockng enable iLOCKen iLOCK 0.7·VDD V voltage
DS13652
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Rev 1 page 6/23
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and ‘safe state’ 6.3 Control Inputs 6.4 Watchdog 6.5 Thermal shutdown protection 6.6 Standby function 6.7 Interlocking function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-36W package information 11 Suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures