Datasheet ADG619-EP (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | CMOS, ±5 V/+5 V, 4 Ω, Single SPDT Switch |
| Pages / Page | 12 / 8 — ADG619-EP. TEST CIRCUITS. IDS. S (OFF). D (OFF). ID (ON). ON = V1/ IDS. … |
| File Format / Size | PDF / 226 Kb |
| Document Language | English |
ADG619-EP. TEST CIRCUITS. IDS. S (OFF). D (OFF). ID (ON). ON = V1/ IDS. VDD VSS. 0.1µF. 50%. VIN. 90%. OUT. 300Ω. 35pF. GND. tON. tOFF. VSS. VS1. VOUT. tBBM. VDD
Model Line for this Datasheet
Text Version of Document
ADG619-EP TEST CIRCUITS IDS V1 I I S (OFF) D (OFF) ID (ON) S D S D S D
009
A A NC A V
011
S V V
010
V R S D D ON = V1/ IDS
08844- 08844- 08844- Figure 9. On Resistance Figure 10. Off Leakage Figure 11. On Leakage
VDD VSS 0.1µF 0.1µF 50% 50% VDD VSS VIN S D V 90% 90% OUT V IN RL C S L 300Ω V 35pF OUT
012
GND tON tOFF
08844- Figure 12. Switching Times
VDD VSS 0.1µF 0.1µF V 50% 50% V IN DD VSS 0V S1 VS1 D D2 VOUT 90% 90% S2 V R C V S2 L2 L2 OUT 0V IN 300Ω 35pF V GND
013
IN tBBM tBBM
08844- Figure 13. Break-Before-Make Time Delay, tBBM
VDD VSS VDD VSS VIN RS D S VOUT S2 C ΔVOUT V L S IN 1nF VOUT GND ΔVOUT
014
S1 QINJ = CL × ΔVOUT
08844- Figure 14. Charge Injection
V V DD SS 0.1µF 0.1µF NETWORK VDD V ANALYZER SS S 50Ω IN 50Ω VS D VOUT VIN RL 50Ω GND V
015
OUT OFF ISOLATION = 20 log VS
08844- Figure 15. Off Isolation Rev. 0 | Page 8 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Dual Supply Single Supply Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Outline Dimensions Ordering Guide
009
A A NC A V
011
S V V
010
V R S D D ON = V1/ IDS
08844- 08844- 08844- Figure 9. On Resistance Figure 10. Off Leakage Figure 11. On Leakage
VDD VSS 0.1µF 0.1µF 50% 50% VDD VSS VIN S D V 90% 90% OUT V IN RL C S L 300Ω V 35pF OUT
012
GND tON tOFF
08844- Figure 12. Switching Times
VDD VSS 0.1µF 0.1µF V 50% 50% V IN DD VSS 0V S1 VS1 D D2 VOUT 90% 90% S2 V R C V S2 L2 L2 OUT 0V IN 300Ω 35pF V GND
013
IN tBBM tBBM
08844- Figure 13. Break-Before-Make Time Delay, tBBM
VDD VSS VDD VSS VIN RS D S VOUT S2 C ΔVOUT V L S IN 1nF VOUT GND ΔVOUT
014
S1 QINJ = CL × ΔVOUT
08844- Figure 14. Charge Injection
V V DD SS 0.1µF 0.1µF NETWORK VDD V ANALYZER SS S 50Ω IN 50Ω VS D VOUT VIN RL 50Ω GND V
015
OUT OFF ISOLATION = 20 log VS
08844- Figure 15. Off Isolation Rev. 0 | Page 8 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Dual Supply Single Supply Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Outline Dimensions Ordering Guide
