Datasheet BlueNRG-LPS (STMicroelectronics) - 3
| Manufacturer | STMicroelectronics |
| Description | Programmable Bluetooth Low Energy Wireless SoC |
| Pages / Page | 63 / 3 — BlueNRG-LPS. Applications. Description. DS13819. Rev 2. page 3/63 |
| File Format / Size | PDF / 8.2 Mb |
| Document Language | English |
BlueNRG-LPS. Applications. Description. DS13819. Rev 2. page 3/63
Model Line for this Datasheet
Text Version of Document
BlueNRG-LPS Applications
• Industrial • Home and industrial automation • Asset tracking, ID location, real-time locating system • Smart lighting • Fitness,wellness and sports • Healthcare, consumer medical • Security/proximity • Remote control • Assisted living • Mobile phone peripherals • PC peripherals
Description
The BlueNRG-LPS is an ultra-low power programmable Bluetooth® Low Energy wireless SoC solution. It embeds STMicroelectronics’s state-of-the-art 2.4 GHz radio IPs, optimized for ultra-low-power consumption and excellent radio performance, for unparalleled battery lifetime. It is compliant with Bluetooth® Low Energy SIG core specification version 5.3 addressing point-to-point connectivity and Bluetooth Mesh networking and allows large-scale device networks to be established in a reliable way. The BlueNRG-LPS is also suitable for 2.4 GHz proprietary radio wireless communication to address ultra-low latency applications. The BlueNRG-LPS embeds a Arm® Cortex®-M0+ microcontroller that can operate up to 64 MHz and also the BlueNRG core co-processor (DMA based) for Bluetooth Low Energy timing critical operations. The main Bluetooth® Low Energy 5.3 specification supported features are: 2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection algorithm #2, GATT caching, Direction Finding (AoA/AoD), hardware support for simultaneous connection, master/slave and multiple roles simultaneously, extended packet length support, LE Ping procedure, periodic advertising and periodic advertising sync transfer, LE power control and path loss monitoring. In addition, the BlueNRG-LPS provides enhanced security hardware support by dedicated hardware functions: True random number generator (RNG), encryption AES maximum 128-bit security co-processor, public key accelerator (PKA), CRC calculation unit, 64-bit unique ID, Flash memory read and write protection. The Public Key Acceleration (PKA) supports the modular arithmetic including exponentiation with maximum modulo size of 3136 bits and the elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits CRC calculation unit. The BlueNRG-LPS can be configured to support standalone or network processor applications. In the first configuration, the BlueNRG-LPS operates as a single device in the application for managing both the application code and the Bluetooth Low Energy stack. The BlueNRG-LPS embeds high-speed and flexible memory types: Flash memory of 192 kB, RAM memory of 24 kB, one-time-programmable (OTP) memory area of 1 kB, ROM memory of 7 kB. Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The BlueNRG-LPS embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to three internal sources, including battery monitoring and a temperature sensor. The BlueNRG-LPS has a low-power RTC and three general purpose 16-bit timers. The BlueNRG-LPS features standard and advanced communication interfaces: 1x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA and Modbus mode, 1x I2C supporting SMBus/PMBus. The BlueNRG-LPS operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The BlueNRG-LPS integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with a fixed threshold that generates a device reset when the VDD drops under 1.65 V. The BlueNRG-LPS comes in different package versions supporting up to:
DS13819
-
Rev 2 page 3/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history
• Industrial • Home and industrial automation • Asset tracking, ID location, real-time locating system • Smart lighting • Fitness,wellness and sports • Healthcare, consumer medical • Security/proximity • Remote control • Assisted living • Mobile phone peripherals • PC peripherals
Description
The BlueNRG-LPS is an ultra-low power programmable Bluetooth® Low Energy wireless SoC solution. It embeds STMicroelectronics’s state-of-the-art 2.4 GHz radio IPs, optimized for ultra-low-power consumption and excellent radio performance, for unparalleled battery lifetime. It is compliant with Bluetooth® Low Energy SIG core specification version 5.3 addressing point-to-point connectivity and Bluetooth Mesh networking and allows large-scale device networks to be established in a reliable way. The BlueNRG-LPS is also suitable for 2.4 GHz proprietary radio wireless communication to address ultra-low latency applications. The BlueNRG-LPS embeds a Arm® Cortex®-M0+ microcontroller that can operate up to 64 MHz and also the BlueNRG core co-processor (DMA based) for Bluetooth Low Energy timing critical operations. The main Bluetooth® Low Energy 5.3 specification supported features are: 2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection algorithm #2, GATT caching, Direction Finding (AoA/AoD), hardware support for simultaneous connection, master/slave and multiple roles simultaneously, extended packet length support, LE Ping procedure, periodic advertising and periodic advertising sync transfer, LE power control and path loss monitoring. In addition, the BlueNRG-LPS provides enhanced security hardware support by dedicated hardware functions: True random number generator (RNG), encryption AES maximum 128-bit security co-processor, public key accelerator (PKA), CRC calculation unit, 64-bit unique ID, Flash memory read and write protection. The Public Key Acceleration (PKA) supports the modular arithmetic including exponentiation with maximum modulo size of 3136 bits and the elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits CRC calculation unit. The BlueNRG-LPS can be configured to support standalone or network processor applications. In the first configuration, the BlueNRG-LPS operates as a single device in the application for managing both the application code and the Bluetooth Low Energy stack. The BlueNRG-LPS embeds high-speed and flexible memory types: Flash memory of 192 kB, RAM memory of 24 kB, one-time-programmable (OTP) memory area of 1 kB, ROM memory of 7 kB. Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The BlueNRG-LPS embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to three internal sources, including battery monitoring and a temperature sensor. The BlueNRG-LPS has a low-power RTC and three general purpose 16-bit timers. The BlueNRG-LPS features standard and advanced communication interfaces: 1x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA and Modbus mode, 1x I2C supporting SMBus/PMBus. The BlueNRG-LPS operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The BlueNRG-LPS integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with a fixed threshold that generates a device reset when the VDD drops under 1.65 V. The BlueNRG-LPS comes in different package versions supporting up to:
DS13819
-
Rev 2 page 3/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history
