Datasheet EFM8SB1 (Silicon Labs) - 8
| Manufacturer | Silicon Labs |
| Description | EFM8 Sleepy Bee Family |
| Pages / Page | 71 / 8 — Timers (Timer 0, Timer 1, Timer 2, and Timer 3). Watchdog Timer (WDT0). … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Timers (Timer 0, Timer 1, Timer 2, and Timer 3). Watchdog Timer (WDT0). 3.6 Communications and Other Digital Peripherals
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Text Version of Document
EFM8SB1 Data Sheet System Overview
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter- vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities. Timer 0 and Timer 1 include the following features: • Standard 8051 timers, supporting backwards-compatibility with firmware and hardware. • Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin. • 8-bit auto-reload counter/timer mode • 13-bit counter/timer mode • 16-bit counter/timer mode • Dual 8-bit counter/timer mode (Timer 0) Timer 2 and Timer 3 are 16-bit timers including the following features: • Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8. • 16-bit auto-reload timer mode • Dual 8-bit auto-reload timer mode • Comparator 0 or RTC0 capture (Timer 2) • RTC0 or EXTCLK/8 capture (Timer 3)
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by system software. The state of the RSTb pin is unaffected by this reset. The Watchdog Timer integrated in the PCA0 peripheral has the following features: • Programmable timeout interval • Runs from the selected PCA clock source • Automatically enabled after any system reset
3.6 Communications and Other Digital Peripherals Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. The UART module provides the following features: • Asynchronous transmissions and receptions. • Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive). • 8- or 9-bit data. • Automatic start and stop generation. • Single-byte FIFO on transmit and receive.
silabs.com
| Building a more connected world. Rev. 1.4 | 7 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter- vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities. Timer 0 and Timer 1 include the following features: • Standard 8051 timers, supporting backwards-compatibility with firmware and hardware. • Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin. • 8-bit auto-reload counter/timer mode • 13-bit counter/timer mode • 16-bit counter/timer mode • Dual 8-bit counter/timer mode (Timer 0) Timer 2 and Timer 3 are 16-bit timers including the following features: • Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8. • 16-bit auto-reload timer mode • Dual 8-bit auto-reload timer mode • Comparator 0 or RTC0 capture (Timer 2) • RTC0 or EXTCLK/8 capture (Timer 3)
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by system software. The state of the RSTb pin is unaffected by this reset. The Watchdog Timer integrated in the PCA0 peripheral has the following features: • Programmable timeout interval • Runs from the selected PCA clock source • Automatically enabled after any system reset
3.6 Communications and Other Digital Peripherals Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. The UART module provides the following features: • Asynchronous transmissions and receptions. • Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive). • 8- or 9-bit data. • Automatic start and stop generation. • Single-byte FIFO on transmit and receive.
silabs.com
| Building a more connected world. Rev. 1.4 | 7 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents
