Datasheet NCV5230 (ON Semiconductor) - 5

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NCV5230 THEORY OF OPERATION Input Stage
voltage moves from the range where only the NPN pair was Operational amplifiers which are able to function at operating to where both of the input pairs were operating, the minimum supply voltages should have input and output effective transconductance would change by a factor of two. stage swings capable of reaching both supply voltages Frequency compensation for the ranges where one input pair within a few millivolts in order to achieve ease of quiescent was operating would, of course, not be optimal for the range biasing and to have maximum input/output signal handling where both pairs were operating. Secondly, fast changes in capability. The input stage of the NCV5230 has a the common−mode voltage would abruptly saturate and common−mode voltage range that not only includes the restore the emitter current sources, causing transient entire supply voltage range, but also allows either supply to distortion. These problems were overcome by assuring that be exceeded by 250 mV without increasing the input offset only the input transistor pair which is able to function voltage by more than 6.0 mV. This is unequalled by any properly is active. The NPN pair is normally activated by the other operational amplifier today. current source IB1 through Q5 and the current mirror Q6 and In order to accomplish the feat of rail−to−rail input Q7, assuming the PNP pair is non−conducting. When the common−mode range, two emitter−coupled differential common−mode input voltage passes below the reference pairs are placed in parallel so that the common−mode voltage, VB1 − 0.8 V at the base of Q5, the emitter current is voltage of one can reach the positive supply rail and the other gradually steered toward the PNP pair, away from the NPN can reach the negative supply rail. The simplified schematic pair. The transfer of the emitter currents between the of Figure 1 shows how the complementary emitter−coupler complementary input pairs occurs in a voltage range of transistors are configured to form the basic input stage cell. about 120 mV around the reference voltage VB1. In this way Common−mode input signal voltages in the range from the sum of the emitter currents for each of the NPN and PNP 0.8 V above VEE to VCC are handled completely by the NPN transistor pairs is kept constant; this ensures that the pair, Q3 and Q4, while common−mode input signal voltages transconductance of the parallel combination will be in the range of VEE to 0.8 V above VEE are processed only constant, since the transconductance of bipolar transistors is by the PNP pair, Q1 and Q2. The intermediate range of input proportional to their emitter currents. voltages requires that both the NPN and PNP pairs are An essential requirement of this kind of input stage is to operating. The collector currents of the input transistors are minimize the changes in input offset voltage between that of summed by the current combiner circuit composed of the NPN and PNP transistor pair which occurs when the transistors Q8 through Q11 into one output current. input common−mode voltage crosses the internal reference Transistor Q8 is connected as a diode to ensure that the voltage, VB1. Careful circuit layout with a cross−coupled outputs of Q2 and Q4 are properly subtracted from those of quad for each input pair has yielded a typical input offset Q1 and Q3. voltage of less than 0.3 mV and a change in the input offset The input stage was designed to overcome two important voltage of less than 0.1 mV. problems for rail−to−rail capability. As the common−mode VCC R10 R11 + V Vb2 Q10 Q11 Ib1 Q3 VIN− Q1 Q2 Q4 VIN+ IOUT Q5 Q8 Q9 + V Vb1 Q6 Q7 R8 R9 VEE
Figure 1. Input Stage www.onsemi.com 5