Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 2
| Manufacturer | Efficient Power Conversion |
| Description | ePower Stage IC |
| Pages / Page | 15 / 2 — eGaN® FET DATASHEET. Figure 2: EPC23102 Quad Flat No-Lead (QFN). Package … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
eGaN® FET DATASHEET. Figure 2: EPC23102 Quad Flat No-Lead (QFN). Package (Transparent Top View). Pin. Description
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eGaN® FET DATASHEET
EPC23102
Figure 2: EPC23102 Quad Flat No-Lead (QFN) Package (Transparent Top View) Pin Description 1
HSIN
2
LSIN
3
EN
10 9 8 4
VDD
5
VDRV
6
RDRV
7
AGND
8
PGND
9
SW
7 10
V
11
IN
6 11
VPHASE
12 12
RBOOT
13
V
13
BOOT
1 2 3 4 5 EPC23102 Pinout Description Transparent Top View Pin Pin Name Pin Type Description 1
HSIN L High side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between HSIN and AGND.
2
LSIN L Low side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between LSIN and AGND. VDD disable input, level referenced to AGND. Internal VDD will be disabled
3
EN L when EN is pulled up to VDRV or external 5 V source. Internal pull-down resistor is connected between EN and AGND, thereby VDD will follow VDRV with EN connected to AGND by default.
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from VDD to AGND.
5
VDRV S External 5 V nominal power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
6
RDRV G Insert resistor between RDRV to VDRV to control the turn-on slew rate of the driven low side FET. Logic ground. Connect bypass capacitors between operating bias supplies,
7
AGND S VDRV and VDD, to AGND. Internal IC connection between AGND and PGND. Use star ground external connection with PGND to system ground.
8
PGND P Input power supply ground return. Connected to source terminal of internal low side FET. Connect power loop capacitors from VIN to PGND. Output switching node. Connected to output of half-bridge power stage.
9
SW P SW pin connects together the source terminal of high side FET and the drain terminal of the low side FET. Power bus input. Connected to drain terminal of internal high side FET.
10
VIN P Connect power loop capacitors from VIN to PGND or power source terminals of low side FET.
11
VPHASE S Kelvin connection to SW, the output switching node. The floating bootstrap power supply, VBOOT , is also referenced to VPHASE.
12
RBOOT G Insert resistor between RBOOT to VBOOT to control the turn-on slew rate of the internal high side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bypass capacitor from VBOOT to VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
EPC23102
Figure 2: EPC23102 Quad Flat No-Lead (QFN) Package (Transparent Top View) Pin Description 1
HSIN
2
LSIN
3
EN
10 9 8 4
VDD
5
VDRV
6
RDRV
7
AGND
8
PGND
9
SW
7 10
V
11
IN
6 11
VPHASE
12 12
RBOOT
13
V
13
BOOT
1 2 3 4 5 EPC23102 Pinout Description Transparent Top View Pin Pin Name Pin Type Description 1
HSIN L High side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between HSIN and AGND.
2
LSIN L Low side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between LSIN and AGND. VDD disable input, level referenced to AGND. Internal VDD will be disabled
3
EN L when EN is pulled up to VDRV or external 5 V source. Internal pull-down resistor is connected between EN and AGND, thereby VDD will follow VDRV with EN connected to AGND by default.
4
VDD S Internal power supply referenced to AGND, connect a bypass capacitor from VDD to AGND.
5
VDRV S External 5 V nominal power supply referenced to AGND, connect a bypass capacitor from VDRV to AGND.
6
RDRV G Insert resistor between RDRV to VDRV to control the turn-on slew rate of the driven low side FET. Logic ground. Connect bypass capacitors between operating bias supplies,
7
AGND S VDRV and VDD, to AGND. Internal IC connection between AGND and PGND. Use star ground external connection with PGND to system ground.
8
PGND P Input power supply ground return. Connected to source terminal of internal low side FET. Connect power loop capacitors from VIN to PGND. Output switching node. Connected to output of half-bridge power stage.
9
SW P SW pin connects together the source terminal of high side FET and the drain terminal of the low side FET. Power bus input. Connected to drain terminal of internal high side FET.
10
VIN P Connect power loop capacitors from VIN to PGND or power source terminals of low side FET.
11
VPHASE S Kelvin connection to SW, the output switching node. The floating bootstrap power supply, VBOOT , is also referenced to VPHASE.
12
RBOOT G Insert resistor between RBOOT to VBOOT to control the turn-on slew rate of the internal high side FET.
13
VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bypass capacitor from VBOOT to VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
