Datasheet MAX78000 (Analog Devices) - 10

MAX78000 Artificial Intelligence Microcontroller with Ultra-Low- Power Convolutional Neural Network Accelerator
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +105°C. TYP specifications are provided for TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Dynamic, IPO enabled, fSYS_CLK(MAX) = 100MHz, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, ECC disabled, all IREGI_DSLP 22.5 μA/MHz CNN quadrants disabled, all CNN memory disabled, standard DMA with 2 channels active; inputs tied to VSS, VREGI Current, SLEEP VDDIO, or VDDIOH; outputs source/sink Mode 0mA Fixed, IPO enabled, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, IREGI_FSLP 1.5 mA ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA Dynamic, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 powered off, RV32 in ACTIVE mode, f I SYS_CLK(MAX) = REGI_DLP 18.3 μA/MHz 60MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/ VREGI Current, LOW sink 0mA POWER Mode Fixed, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 powered off, RV32 IREGI_FLP in ACTIVE mode 0MHz, all CNN 0.64 mA quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA Dynamic, ERTCO enabled, IBRO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = VREGI Current, MICRO 1.1V, LPUART active, f I LPUART = 230 μA POWER Mode REGI_DMP 32.768kHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/ sink 0mA Fixed, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = VREGI Current, 1.1V, all CNN quadrants disabled, all I 11.3 μA STANDBY Mode REGI_STBY CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/ sink 0mA www.maximintegrated.com Maxim Integrated | 10 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 81-CTBGA Electrical Characteristics Electrical Characteristics (continued) Electrical Characteristics—SPI Electrical Characteristics—SPI (continued) Electrical Characteristics—I2C Electrical Characteristics—I2C (continued) Electrical Characteristics—I2S Electrical Characteristics—I2S (continued) Electrical Characteristics—PCIF Electrical Characteristics—1-Wire Master Electrical Characteristics—1-Wire Master (continued) Pin Configuration 81 CTBGA Pin Description 81 CTBGA Detailed Description Arm Cortex-M4 with FPU Processor and RISC-V RV32 Processor Convolutional Neural Network Accelerator (CNN) Memory Internal Flash Memory Internal SRAM Comparators Dynamic Voltage Scaling (DVS) Controller Clocking Scheme General-Purpose I/O and Special Function Pins Parallel Camera Interface (PCIF) Analog-to-Digital Converter Single-Inductor Multiple-Output Switch-Mode Power Supply (SIMO SMPS) Power Management Power Management Unit ACTIVE Mode SLEEP Mode LOW POWER Mode (LPM) MICRO POWER Mode (μPM) STANDBY Mode BACKUP Mode POWER DOWN Mode (PDM) Wakeup Sources Real-Time Clock Programmable Timers 32-Bit Timer/Counter/PWM (TMR, LPTMR) Watchdog Timer (WDT) Pulse Train Engine (PT) Serial Peripherals I2C Interface (I2C) I2S Interface (I2S) Serial Peripheral Interface (SPI) UART (UART, LPUART) 1-Wire Master (OWM) Standard DMA Controller Security AES True Random Number Generator (TRNG) Non-Deterministic Random Bit Generator (NDRBG) CRC Module Bootloader Secure Boot Debug and Development Interface (SWD, JTAG) Applications Information Bypass Capacitors Ordering Information Revision History