Datasheet TOP242, TOP243, TOP244, TOP245, TOP246, TOP247, TOP248, TOP249, TOP250 (Power Integrations) - 8

TOP242-250
and 100% of the default current limit. Please refer to the storage capacitor present in applications such as standby graphs in the typical performance characteristics section supplies. A single resistor connected from the LINE- for the selection of the resistor value. By setting current limit SENSE pin (Y, R or F package) or MULTI-FUNCTION pin low, a larger TOPSwitch-GX than necessary for the power (P or G package) to the rectified DC high voltage bus sets required can be used to take advantage of the lower R UV threshold during power up. Once the power supply DS(ON) for higher efficiency/smaller heat sinking requirements. is successfully turned on, the UV threshold is lowered to With a second resistor connected between the EXTERNAL 40% of the initial UV threshold to allow extended input CURRENT LIMIT (X) pin (Y, R or F package) or MULTI- voltage operating range (UV low threshold). If the UV low FUNCTION (M) pin (P or G package) and the rectified DC threshold is reached during operation without the power high voltage bus, the current limit is reduced with increasing supply losing regulation, the device will turn off and stay line voltage, allowing a true power limiting operation against off until UV (high threshold) has been reached again. If the line variation to be implemented. When using an RCD power supply loses regulation before reaching the UV low clamp, this power limiting technique reduces maximum threshold, the device will enter auto-restart. At the end of clamp voltage at high line. This allows for higher reflected each auto-restart cycle (S7), the UV comparator is enabled. voltage designs as well as reducing clamp dissipation. If the UV high threshold is not exceeded the MOSFET will be disabled during the next cycle (see Figure 8). The UV The leading edge blanking circuit inhibits the current limit feature can be disabled independent of the OV feature as comparator for a short time after the output MOSFET is shown in Figures 19 and 23. turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes
Line Overvoltage Shutdown (OV)
caused by primary-side capacitances and secondary-side The same resistor used for UV also sets an overvoltage rectifier reverse recovery time should not cause premature threshold which, once exceeded, will force TOPSwitch-GX termination of the switching pulse. output into off-state. The ratio of OV and UV thresholds is preset at 4.5 as can be seen in Figure 11. When the The current limit is lower for a short period after the leading MOSFET is off, the rectified DC high voltage surge capability edge blanking time as shown in Figure 52. This is due to is increased to the voltage rating of the MOSFET (700 V), dynamic characteristics of the MOSFET. To avoid triggering due to the absence of the reflected voltage and leakage the current limit in normal operation, the drain current spikes on the drain. A small amount of hysteresis is provided waveform should stay within the envelope shown. on the OV threshold to prevent noise triggering. The OV
Line Undervoltage Detection (UV)
feature can be disabled independent of the UV feature as At power up, UV keeps TOPSwitch-GX off until the input shown in Figures 18 and 32. line voltage reaches the undervoltage threshold. At
Line Feed-Forward with DC Reduction
power down, UV prevents auto-restart attempts after
MAX
The same resistor used for UV and OV also implements the output goes out of regulation. This eliminates power line voltage feed-forward, which minimizes output line down glitches caused by slow discharge of the large input ripple and reduces power supply output sensitivity to line Oscillator (SAW) DMAX Enable from X, L or M Pin (STOP)
Time
PI-2637-060600 Figure 10. Synchronization Timing Diagram.
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Rev. R 10/20 www.power.com