Datasheet LSJ689 (Linear Systems)
| Manufacturer | Linear Systems |
| Description | Low Noise Low Capacitance Monolithic Dual P-Channel JFET Amplifier |
| Pages / Page | 6 / 1 — LSJ689. LOW NOISE LOW CAPACITANCE. MONOLITHIC DUAL. P-CHANNEL JFET … |
| File Format / Size | PDF / 604 Kb |
| Document Language | English |
LSJ689. LOW NOISE LOW CAPACITANCE. MONOLITHIC DUAL. P-CHANNEL JFET AMPLIFIER. FEATURES. Features. Benefits. Applications. Description
Model Line for this Datasheet
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LSJ689 LOW NOISE LOW CAPACITANCE MONOLITHIC DUAL P-CHANNEL JFET AMPLIFIER FEATURES
ULTRA LOW NOISE en = 2.0nV/√Hz LOW INPUT CAPACITANCE Ciss = 8pF
Features Benefits Applications
• Reduced Noise due • Tight differential voltage match vs. • Wide band differential Amps to process improvement current • High speed temperature • Monolithic Design • Improved op amp speed settling time compensated single ended input • High slew rate accuracy amplifier amps • Low offset/drift voltage • Minimum Input Error trimming error • High speed comparators • Low gate leakage lgss & lg voltage • Impedance Converters • High CMRR 102 dB • Lower intermodulation distortion
Description
The LSJ689 high performance, P-Channel, monolithic dual JFET features extremely low noise, tight offset voltage and low drift over temperature. It is targeted for use in a wide range of precision instrumentation applications. The SOT-23, TO-71 and SO-8 packages provide ease of manufacturing and the symmetrical pinouts prevent improper orientation. The SOT-23 and SO-8 packages are available in tape and reel, compatible with automatic assembly methods. (See packaging data)
ABSOLUTE MAXIMUM RATINGS1
@ 25 °C (unless otherwise stated)
SOIC-A Maximum Temperatures TOP VIEW
Storage Temperature -55 to +150°C Junction Operating Temperature -55 to +150°C
TO-71 Maximum Power Dissipation, TA = 25°C TOP VIEW
Continuous Power Dissipation, per side 4 300mW Power Dissipation, total 5 500mW
Maximum Currents SOT-23
Gate Forward Current IG(F) = -10mA
TOP VIEW Maximum Voltages
Gate to Source VGS = 50V Gate to Drain VGD = 50V Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 07/23/19 Rev#A9 ECN# LSJ689
ULTRA LOW NOISE en = 2.0nV/√Hz LOW INPUT CAPACITANCE Ciss = 8pF
Features Benefits Applications
• Reduced Noise due • Tight differential voltage match vs. • Wide band differential Amps to process improvement current • High speed temperature • Monolithic Design • Improved op amp speed settling time compensated single ended input • High slew rate accuracy amplifier amps • Low offset/drift voltage • Minimum Input Error trimming error • High speed comparators • Low gate leakage lgss & lg voltage • Impedance Converters • High CMRR 102 dB • Lower intermodulation distortion
Description
The LSJ689 high performance, P-Channel, monolithic dual JFET features extremely low noise, tight offset voltage and low drift over temperature. It is targeted for use in a wide range of precision instrumentation applications. The SOT-23, TO-71 and SO-8 packages provide ease of manufacturing and the symmetrical pinouts prevent improper orientation. The SOT-23 and SO-8 packages are available in tape and reel, compatible with automatic assembly methods. (See packaging data)
ABSOLUTE MAXIMUM RATINGS1
@ 25 °C (unless otherwise stated)
SOIC-A Maximum Temperatures TOP VIEW
Storage Temperature -55 to +150°C Junction Operating Temperature -55 to +150°C
TO-71 Maximum Power Dissipation, TA = 25°C TOP VIEW
Continuous Power Dissipation, per side 4 300mW Power Dissipation, total 5 500mW
Maximum Currents SOT-23
Gate Forward Current IG(F) = -10mA
TOP VIEW Maximum Voltages
Gate to Source VGS = 50V Gate to Drain VGD = 50V Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201180 07/23/19 Rev#A9 ECN# LSJ689
