Datasheet IKCM15F60GA (Infineon) - 5

Control Integrated POwer System (CIPOS™) IKCM15F60GA Pin Assignment Pin Number Pin Name Pin Description 1 VS(U) U-phase high side floating IC supply offset voltage 2 VB(U) U-phase high side floating IC supply voltage 3 VS(V) V-phase high side floating IC supply offset voltage 4 VB(V) V-phase high side floating IC supply voltage 5 VS(W) W-phase high side floating IC supply offset voltage 6 VB(W) W-phase high side floating IC supply voltage 7 HIN(U) U-phase high side gate driver input 8 HIN(V) V-phase high side gate driver input 9 HIN(W) W-phase high side gate driver input 10 LIN(U) U-phase low side gate driver input 11 LIN(V) V-phase low side gate driver input 12 LIN(W) W-phase low side gate driver input 13 VDD Low side control supply 14 VFO Fault output / Temperature monitor 15 ITRIP Over current shutdown input 16 VSS Low side control negative supply 17 NW W-phase low side emitter 18 NV V-phase low side emitter 19 NU U-phase low side emitter 20 W Motor W-phase output 21 V Motor V-phase output 22 U Motor U-phase output 23 P Positive bus input voltage 24 NC No Connection Pin Description HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 - 12) These pins are positive logic and they are CIPOSTM responsible for the control of the integrated IGBT. Schmitt-Trigger The Schmitt-trigger input thresholds of them are HINx INPUT NOISE LINx such to guarantee LSTTL and CMOS compatibility FILTER U  Z=10.5V k 5 SWITCH LEVEL down to 3.3V controller outputs. Pull-down resistor VSS VIH; VIL of about 5k is internally provided to pre-bias Figure 3 Input pin structure inputs during supply start-up and a zener clamp is provided for pin protection purposes. Input a) t b) t FILIN FILIN Schmitt-trigger and noise filter provide beneficial noise rejection to short input pulses. HIN HIN LIN LIN The noise filter suppresses control pulses which are high HO HO below the filter time t LO low LO FILIN. The filter acts according to Figure 4. Figure 4 Input filter timing diagram Datasheet 5 of 17 V 2.5 2017-09-06 Document Outline Table of contents CIPOS™ Control Integrated POwer System Features Target Applications Description System Configuration Pin Configuration Internal Electrical Schematic Pin Assignment Pin Description HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 - 12) VFO (Fault-output and NTC, Pin 14) ITRIP (Over current detection function, Pin 15) VDD, VSS (Low side control supply and reference, Pin 13, 16) VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 1 - 6) NW, NV, NU (Low side emitter, Pin 17 - 19) W, V, U (High side emitter and low side collector, Pin 20 - 22) P (Positive bus input voltage, Pin 23) Absolute Maximum Ratings Module Section Inverter Section Control Section Recommended Operation Conditions Static Parameters Dynamic Parameters Bootstrap Parameters Thermistor Mechanical Characteristics and Ratings Circuit of a Typical Application Switching Times Definition Electrical characteristic Package Outline Revision history