Datasheet TPLD1201 (Texas Instruments)
| Manufacturer | Texas Instruments |
| Description | Programmable Logic Device With Eight General Purpose Input Or Outputs (GPIOs) |
| Pages / Page | 67 / 1 — TPLD1201. TPLD1201 Programmable Logic Device with 8-GPIO. 1 Features. 3 … |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
TPLD1201. TPLD1201 Programmable Logic Device with 8-GPIO. 1 Features. 3 Description. Device Information. PART NUMBER. PACKAGE
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TPLD1201
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
TPLD1201 Programmable Logic Device with 8-GPIO 1 Features 3 Description
• Operating characteristics The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile – Extended temperature range: -40°C to 125°C programmable logic ICs with combinational logic, – Wide supply voltage range: 1.71V to 5.5V sequential logic, and analog blocks. TPLD provides • Configurable macro-cells a fully integrated, low power solution to implement common system functions, such as timing delays, – 2-, 3-, and 4-bit lookup tables voltage monitors, system resets, power sequencers, – D-type flip-flops and latches with and without I/O expanders, and more. This device features reset/set option configurable I/O structures that extends compatibility – 8-bit pipe delay within mixed-signal environments, reducing the – Counters and delay generator number of discrete components required. – Programmable deglitch filter or edge detector – Discrete analog comparators System designers can create circuits and configure – Voltage reference the macro-cells, I/O pins, and interconnections – Oscillator by temporarily emulating the non-volatile memory or by permanently programming the one-time • Flexible digital I/O features programmable (OTP) through InterConnect Studio. – All digital signals can be routed to any GPIO The TPLD1201 is supported by a hardware and – Digital input modes: digital in with and without software ecosystem with application notes, reference Schmitt-trigger, low-voltage digital in designs, and design examples. Visit ti.com for more – Digital output modes: push-pull, open-drain information and access to design tools. NMOS, tri-state
Device Information
• Development tools
PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
– InterConnect Studio DGS (VSSOP, 10)(2) 4.9mm × 3.0mm TPLD1201 – TPLD1201 evaluation module RWB (X2QFN, 12) 1.6mm × 1.6mm – TPLD programming board (1) For all available packages, see the orderable addendum at
2 Applications
the end of the datasheet. (2) Product Preview. • Factory automation and control D • Communications equipment RST Q OUT CLK EN (IO) • Retail automation and payment CLK lut dff POW1 (IO) cnt • Test and measurement • Pro audio, video and signage D Q osc CLK • Personal electronics lut dff POW2 (IO) D Q CLK POW3 (IO) dff D Q CLK lut POW4 (IO) dff IN OUT0 OUT NRST lut OUT1 POW5 (IO) CLK por pipedelay
Figure 3-1. Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data
TPLD1201
SCPS287B – NOVEMBER 2023 – REVISED DECEMBER 2024
TPLD1201 Programmable Logic Device with 8-GPIO 1 Features 3 Description
• Operating characteristics The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile – Extended temperature range: -40°C to 125°C programmable logic ICs with combinational logic, – Wide supply voltage range: 1.71V to 5.5V sequential logic, and analog blocks. TPLD provides • Configurable macro-cells a fully integrated, low power solution to implement common system functions, such as timing delays, – 2-, 3-, and 4-bit lookup tables voltage monitors, system resets, power sequencers, – D-type flip-flops and latches with and without I/O expanders, and more. This device features reset/set option configurable I/O structures that extends compatibility – 8-bit pipe delay within mixed-signal environments, reducing the – Counters and delay generator number of discrete components required. – Programmable deglitch filter or edge detector – Discrete analog comparators System designers can create circuits and configure – Voltage reference the macro-cells, I/O pins, and interconnections – Oscillator by temporarily emulating the non-volatile memory or by permanently programming the one-time • Flexible digital I/O features programmable (OTP) through InterConnect Studio. – All digital signals can be routed to any GPIO The TPLD1201 is supported by a hardware and – Digital input modes: digital in with and without software ecosystem with application notes, reference Schmitt-trigger, low-voltage digital in designs, and design examples. Visit ti.com for more – Digital output modes: push-pull, open-drain information and access to design tools. NMOS, tri-state
Device Information
• Development tools
PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
– InterConnect Studio DGS (VSSOP, 10)(2) 4.9mm × 3.0mm TPLD1201 – TPLD1201 evaluation module RWB (X2QFN, 12) 1.6mm × 1.6mm – TPLD programming board (1) For all available packages, see the orderable addendum at
2 Applications
the end of the datasheet. (2) Product Preview. • Factory automation and control D • Communications equipment RST Q OUT CLK EN (IO) • Retail automation and payment CLK lut dff POW1 (IO) cnt • Test and measurement • Pro audio, video and signage D Q osc CLK • Personal electronics lut dff POW2 (IO) D Q CLK POW3 (IO) dff D Q CLK lut POW4 (IO) dff IN OUT0 OUT NRST lut OUT1 POW5 (IO) CLK por pipedelay
Figure 3-1. Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Supply Current Characteristics 5.7 Switching Characteristics 5.8 Typical Characteristics 6 Parameter Measurement Information 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 I/O Pins 7.3.2 Connection Mux 7.3.3 Configurable Use Logic Blocks 7.3.3.1 2-Bit LUT Macro-Cell 7.3.3.2 3-Bit LUT Macro-Cell 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY) 7.3.4.1 Delay Mode 7.3.4.2 Edge Detector Mode 7.3.4.3 Reset Counter Mode 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-cell 7.3.6 Selectable Frequency Oscillator 7.3.7 Analog Comparators (ACMP) 7.3.8 Voltage Reference (VREF) 7.4 Device Functional Modes 7.4.1 Power-On Reset 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.1.1 Power Considerations 8.2.1.2 Input Considerations 8.2.1.3 Output Considerations 8.2.2 Detailed Design Procedure 8.2.3 Application Curves 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Receiving Notification of Documentation Updates 9.2 Support Resources 9.3 Trademarks 9.4 Electrostatic Discharge Caution 9.5 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Option Addendum 11.2 Tape and Reel Information 11.3 Mechanical Data
