Datasheet ADA4961 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Low Distortion, 3.2 GHz, RF DGA |
| Pages / Page | 24 / 3 — Data Sheet. ADA4961. SPECIFICATIONS. Table 1. Parameter. Test … |
| Revision | B |
| File Format / Size | PDF / 904 Kb |
| Document Language | English |
Data Sheet. ADA4961. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADA4961 SPECIFICATIONS
VS = 5 V, HP mode, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for two- tone IMD3), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VO indicates small signal 3200 MHz −1 dB Bandwidth VO indicates small signal 1800 MHz Slew Rate VO = 2 V step 12000 V/μs Settling Time to 1.0% VO = 2 V step 0.6 ns Overdrive Recovery Time 1.2 ns Input Return Loss (S11) 500 MHz −40 dB Output Return Loss (S22) 500 MHz −30 dB GAIN Voltage Gain Maximum voltage gain 15 dB Minimum voltage gain −6 Power Gain Maximum power gain 18 dB Minimum power gain −3 Gain Step Size 1.0 dB Gain Step Error ±0.2 dB INPUT STAGE Input Common-Mode Voltage 1.0 V Input Resistance Differential 100 Ω Maximum AC-Coupled Input Level Differential 6 V p-p Input Capacitance Single-ended 1.3 pF Common-Mode Rejection Ratio (CMRR) 55 dB OUTPUT STAGE Maximum Output Voltage Swing VS = 5.0 V 5.0 V p-p VS = 3.3 V 3.0 V p-p Differential Output Resistance 50 Ω DIGITAL LOGIC SPECIFICATIONS Input Voltage High, CS1, CLK1, SDIO (VIH) 1.4 3.3 V Input Voltage High, PM (VIH) 2.8 3.3 V Input Voltage Low, CS1, CLK1, SDIO, PM (VIL) 0 0.8 V Output Voltage High, CS1, CLK1, SDIO (VOH) IOH = −100 µA 1.4 3.3 V Output Voltage Low, CS1, CLK1, SDIO (VOL) IOL = +100 µA 0 0.8 V POWER SUPPLY Operating Range 3.3 to 5.0 V Quiescent Current 5.0 V, HP mode 154 mA 5.0 V, low power (LP) mode 131 mA 5.0 V, power-down Mode 7.4 mA 3.3 V, LP mode 126 mA 3.3 V, power-down Mode 7.2 mA 1 Dual function pin. Table 1 does not contain the ful pin name, only the relevant function of the pin. See the Pin Configuration and Function Descriptions section for complete pin names and descriptions. Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADA4961 SPECIFICATIONS
VS = 5 V, HP mode, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for two- tone IMD3), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VO indicates small signal 3200 MHz −1 dB Bandwidth VO indicates small signal 1800 MHz Slew Rate VO = 2 V step 12000 V/μs Settling Time to 1.0% VO = 2 V step 0.6 ns Overdrive Recovery Time 1.2 ns Input Return Loss (S11) 500 MHz −40 dB Output Return Loss (S22) 500 MHz −30 dB GAIN Voltage Gain Maximum voltage gain 15 dB Minimum voltage gain −6 Power Gain Maximum power gain 18 dB Minimum power gain −3 Gain Step Size 1.0 dB Gain Step Error ±0.2 dB INPUT STAGE Input Common-Mode Voltage 1.0 V Input Resistance Differential 100 Ω Maximum AC-Coupled Input Level Differential 6 V p-p Input Capacitance Single-ended 1.3 pF Common-Mode Rejection Ratio (CMRR) 55 dB OUTPUT STAGE Maximum Output Voltage Swing VS = 5.0 V 5.0 V p-p VS = 3.3 V 3.0 V p-p Differential Output Resistance 50 Ω DIGITAL LOGIC SPECIFICATIONS Input Voltage High, CS1, CLK1, SDIO (VIH) 1.4 3.3 V Input Voltage High, PM (VIH) 2.8 3.3 V Input Voltage Low, CS1, CLK1, SDIO, PM (VIL) 0 0.8 V Output Voltage High, CS1, CLK1, SDIO (VOH) IOH = −100 µA 1.4 3.3 V Output Voltage Low, CS1, CLK1, SDIO (VOL) IOL = +100 µA 0 0.8 V POWER SUPPLY Operating Range 3.3 to 5.0 V Quiescent Current 5.0 V, HP mode 154 mA 5.0 V, low power (LP) mode 131 mA 5.0 V, power-down Mode 7.4 mA 3.3 V, LP mode 126 mA 3.3 V, power-down Mode 7.2 mA 1 Dual function pin. Table 1 does not contain the ful pin name, only the relevant function of the pin. See the Pin Configuration and Function Descriptions section for complete pin names and descriptions. Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
