Datasheet CD54HC123, CD74HC123, CD54HCT123, CD74HCT123, CD74HC423, CD74HCT423 (Texas Instruments)

CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Data sheet acquired from Harris Semiconductor SCHS142F
High-Speed CMOS Logic Dual Retriggerable
September 1997 - Revised October 2003
Monostable Multivibrators with Resets Features Ordering Information • Overriding Reset Terminates Output Pulse PART NUMBER TEMP. RANGE (oC) PACKAGE • Triggering From the Leading or Trailing Edge
[ /Title CD54HC123F3A -55 to 125 16 Ld CERDIP
• Q and Q Buffered Outputs
(CD74 CD54HCT123F3A -55 to 125 16 Ld CERDIP
• Separate Resets
HC123
• Wide Range of Output-Pulse Widths
CD74HC123E -55 to 125 16 Ld PDIP ,
• Schmitt Trigger on Both A and B Inputs
CD74HC123M -55 to 125 16 Ld SOIC CD74
• Fanout (Over Temperature Range)
CD74HC123MT -55 to 125 16 Ld SOIC HCT12
- Standard Outputs . 10 LSTTL Loads
CD74HC123M96 -55 to 125 16 Ld SOIC 3,
- Bus Driver Outputs . 15 LSTTL Loads
CD74HC123NSR -55 to 125 16 Ld SOP CD74
• Wide Operating Temperature Range . -55oC to 125oC
HC423 CD74HC123PW -55 to 125 16 Ld TSSOP
• Balanced Propagation Delay and Transition Times
,
• Significant Power Reduction Compared to LSTTL
CD74HC123PWR -55 to 125 16 Ld TSSOP CD74
Logic ICs
CD74HC123PWT -55 to 125 16 Ld TSSOP HCT42
• HC Types
CD74HC423E -55 to 125 16 Ld PDIP 3)
- 2V to 6V Operation
CD74HC423M -55 to 125 16 Ld SOIC /Sub-
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
CD74HC423MT -55 to 125 16 Ld SOIC ject
• HCT Types
CD74HC423M96 -55 to 125 16 Ld SOIC (High
- 4.5V to 5.5V Operation
Speed CD74HC423NSR -55 to 125 16 Ld SOP
- Direct LSTTL Input Logic Compatibility, V
CD74HCT123E -55 to 125 16 Ld PDIP
IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il
≤
1
µ
A at VOL, VOH
CD74HCT123M -55 to 125 16 Ld SOIC
Description
CD74HCT123MT -55 to 125 16 Ld SOIC The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are CD74HCT123M96 -55 to 125 16 Ld SOIC dual monostable multivibrators with resets. They are all CD74HCT423E -55 to 125 16 Ld PDIP retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the CD74HCT423MT -55 to 125 16 Ld SOIC 423 types do not have this feature. An external resistor (RX) CD74HCT423M96 -55 to 125 16 Ld SOIC and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and C NOTE: When ordering, use the entire part number. The suffixes 96 X provides a wide range of output pulse widths from the Q and Q and R denote tape and reel. The suffix T denotes a small-quantity terminals. Pulse triggering on the A and B inputs occur at a reel of 250. particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, Rx is typically 5kΩ. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1