e2v has announced plans to launch a next generation 12-bit ADC that offers 5.4 GSps, low latency and very low noise next year
e2v’s new EV12AS350 is set to be the only 12-bit resolution ADC on the market that combines signal digitization at 5.4 GSps, input bandwidth in excess of 3 GHz and latency as low as 26 clock cycles with a noise of –150 dBm/Hz. Unlike other ADCs on the market, it will be free of non-harmonic spurs, creating a pure signal for coders to manipulate in a range of demanding applications.
With the ability to use a simultaneous sampling mode to average 4 ADC cores and gain 6 dB of Signal to Noise Ratio (SNR), the EV12AS350 will offer high resolution and high dynamic range in one component. These capabilities make it perfect for electronic warfare and test and measurement applications.
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| The EV12AS350 Simplified Block Diagram. |
Richard Gibbs, President of e2v Semiconductors, said, “We have utilized 20 years of e2v knowledge and design disciplines to develop what will be our most powerful ADC to date. Implementing this experience has allowed us to unveil an ADC with no non-harmonic spurs, which will allow coders to achieve previously unimagined performance in their systems.”
Laurent Monge, VP and General Manager of e2v Semiconductors, said, “Very high demand from our customers for the demonstrator of this ADC encouraged us to develop the enhanced version of the EV12AS350 and commit to launching it as a full product that will be available for general sampling next year.”
