Software Allows Customers to Fully Leverage All Architectural Features and Performance of the New Low-Cost Devices and Enables Device Serialization
In conjunction with its introduction of the industry's lowest cost field-programmable gate arrays (FPGAs), Actel Corporation announced that its Libero 6.1 Integrated Design Environment (IDE) provides complete support for the company's new flash-based ProASIC3 and ProASIC3E devices. The Libero 6.1 IDE contains a range of performance, resource optimization and ease-of-use features that, combined with leading third-party design tools, deliver an efficient, seamless flow through simulation, synthesis and place-and-route. The software is optimized to exploit the architectural features of the ProASIC3 and ProASIC3E devices, including the unique on-chip FlashROM (FROM), which can easily be programmed independent of the FPGA core.
Simple Flow Enables the Industry's First FPGA FlashROM Implementation
The Libero IDE applies innovative new technology to help designers take advantage of the FROM function of the ProASIC3/E devices, which can be easily programmed independent of the FPGA core for applications, such as device serialization, Internet Protocol (IP) addressing and version control. A new FlashPoint Programming File Generator integrates preset FROM macros, including device serialization, allowing customers to merge the FPGA configurations and the FROM programming file. The FlashPoint Programming File Generator also enables all encryption capabilities for the FROM contents, such as security header, encryption key and FlashLOCK security. Using the FlashPoint software, designers can change the functionality of the FROM after the completion of the ProASIC3/E design process while preserving the security of the ProASIC3/E core logic.
Actel's ACTgen core builder now provides a comprehensive user interface to ensure simple implementation and seamless flow of various FROM content options into the hardware description language (HDL). Custom FROM applications can be input via a data table or read as a text file. Users can also specify a built-in feature that provides auto increment or decrement during the programming process. This enables each device to have a unique serial number for specialized applications.
Leading-Edge Phase Lock Loop (PLL) Configuration
The ACTgen core builder has a new "Visual PLL" interface that provides a wide range of PLL programming options to dramatically ease the setting of accurate PLL parameters. Using customizable clock conditioning circuitry in the PA3/E devices, the designer can adjust frequency and feedback settings, and set various detailed parameters for clock applications via "tailor-made" PLL schematics.
Optimizing PA3/E Features
The Libero 6.1 IDE includes a MultiView Navigator I/O Attribute Editor that enables easy selection and programming of up to 19 I/O standards within ProASIC3/E devices, thereby streamlining the physical implementation process.
The tool suite offers complete support for the high-speed ProASIC3/E VersaNet Global Network to allow mapping for up to 252 different internal or external clocks within the ProASIC3/E FPGAs. The ChipPlanner, Physical Design Constraints (PDC) and Magma PALACE (Physical and Logical Automatic Compilation Engine) physical synthesis tools provide full support of VersaNet Global Networks, thus simplifying the use of all physical constraint flows. Libero 6.1 Timing Driven Place and Route, coupled with Synplicity's Synplify and Magma's PALACE tools, ensure PA3/E product performance of 66 MHz 64-bit PCI performance — the highest level of performance for any value-based FPGA.
