Brian Benchoff
Hackaday
For almost forty years, integrated circuits have become smaller and smaller. These chips started out with massive transistors in the early 1970s. They shrank to less than 1 μm by 1990, and shrank yet again to less than 100 nm by the turn of the last century. Now, Imec and Cadence are experimenting with 5 nm technology – the smallest technology available for any mass-produced integrated circuit.
The history of microelectronic fabrication over the last decade is a story of failure. Something happened in 2005, and although chips could be designed at ever-smaller technologies, the transition to these smaller manufacturing processes didn’t go as smoothly as in the 70s, 80s, and 90s. Just a few years ago, Intel said 10 nm chips would ship by 2015. These chips are nowhere to be found, and even 14 nm technology is still catching up to the yields found in 22 nm technology. In 2009, Nvidia said their flagship graphics card would be built with a 11 nm process. The current Nvidia flagship desktop graphics card is built with 28 nm technology. Moore’s law isn’t 18 months anymore.
While Imec and Cadence have completed the tapeout on a 5 nm device, it’s just a test chip. Before starting manufacturing on a single process node, Intel and others will tapeout a simple test chip to verify their latest process. This 5 nm tapeout will not become a manufactured chip, but it does mean we’ll see more talk about the 5 nm process in the future.
