K60: Kinetis K60 Low-Power Mixed-Signal MCU from Freescale

The K60 MCU family includes IEEE 1588 Ethernet, full- and high-speed USB 2.0 On-The-Go with device charge detect capability, hardware encryption and tamper detection capabilities. Devices start from 256 KB of flash in 100LQFP packages extending up to 1 MB in a 256MAPBGA package with a rich suite of analog, communication, timing and control peripherals. High memory density K60 family devices include an optional single precision floating point unit, NAND flash controller and DRAM controller.

Common features among the K60 family

• Operating characteristics
  • Voltage range 1.71V - 3.6V
  • Flash memory programming down to 1.71V
  • Temperature range (TA) -40 to 105°C
  • Flexible modes of operation
• Core features
  • Next generation 32-bit ARM Cortex-M4 core
  • Supports DSP instructions
  • Nested vectored interrupt controller (NVIC)
  • Asynchronous wake-up interrupt controller (AWIC)
  • Debug & trace capability
    • 2-pin serial wire debug (SWD)
    • IEEE 1149.1 Joint Test Action Group (JTAG)
    • IEEE 1149.7 compact JTAG (cJTAG)
    • Trace port interface unit (TPIU)
    • Flash patch and breakpoint (FPB)
    • Data watchpoint and trace (DWT)
    • Instrumentation trace macrocell (ITM)
• System and power management
  • Software and hardware watchdog with external monitor pin
  • DMA controller with 16 channels
  • Low-leakage wake-up unit (LLWU)
  • Power management controller with 10 different power modes
  • Non-maskable interrupt (NMI)
  • 128-bit unique identification (ID) number per chip
• Clocks
  • Multi-purpose clock generator
    • PLL and FLL operation
    • Internal reference clocks (32kHz or 2MHz)
  • 12MHz to 32MHz crystal oscillator
  • 32kHz to 40kHz crystal oscillator
  • Internal 1kHz low power oscillator
  • DC to 50MHz external square wave input clock
• Memories and Memory Interfaces
  • FlexMemory consisting of FlexNVM (non-volatile flash memory that can execute program code, store data, or backup EEPROM data) or FlexRAM (RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming)
  • Flash security and protection features
  • NAND flash controller supports up to 32-bit ECC current and future NAND types. ECC management handled in hardware, minimizing software overhead
  • DRAM controller supports connection of DDR, DDR2 and low-power DDR memories. Max. frequency (clock/data) 125/250 MHz
• Security and integrity
  • Hardware Encryption coprocessor for secure data transfer and storage. Faster than software implementations and with minimal CPU loading. Supports a wide variety of algorithms - DES, 3DES, AES, MD5, SHA-1, SHA-256
  • System security and tamper detect with secure real-time clock with independent battery supply. Secure key storage with internal/external tamper detect for unsecure flash, temperature, clock, and supply voltage variations and physical attack detection
  • Memory protection unit provides memory protection for all masters on the cross bar switch, increasing software reliability
  • Cyclic redundancy check engine validates memory contents and communication data, increasing system reliability
  • Independent-clocked COP guards against clock skew or code runaway for fail-safe applications such as the IEC 60730 safety standard for household appliances
• Analog
  • 16-bit SAR ADC
  • Programmable voltage reference (VREF)
  • High-speed Analog comparator (CMP) with 6-bit DAC
• Timers
  • 1×8ch motor control/general purpose/PWM flexible timer (FTM)
  • 1×2ch quadrature decoder/general purpose/PWM flexible timer (FTM)
  • Carrier modulator timer (CMT)
  • Programmable delay block (PDB)
  • 1×4ch programmable interrupt timer (PIT)
  • Low-power timer (LPT)
• Communications
  • SPI
  • I2C with SMBUS support
  • UART (w/ ISO7816, IrDA and hardware flow control)
  • USB 2.0 On-The-Go (full speed). Device charge detect optimizes charging current/time for portable USB devices enabling longer battery life. Low-voltage regulator supplies up to 120 mA off chip at 3.3V to power external components from 5V input
  • IEEE 1588 Ethernet MAC with hardware time stamping provides precision clock synchronization for real-time industrial control
• Human-machine interface
  • GPIO with pin interrupt support, DMA request capability, digital glitch filter, and other pin control options
  • Capacitive touch sensing inputs

K60 Block Diagram

Memory and package options for the K40 family
The following table summarizes the memory and package options for the K40 family. All devices which share a common package are pin-for-pin compatible. 

Perf. MHz	Memory				Package
	Flash (KB)	Flex NVM (KB)	Flex RAM (KB)	SRAM (KB)	100 LQFP	104 BGA	144 LQFP	144 BGA	196 BGA	256 BGA
100	256	-	-	64	+	+	+	+	-	-
	512	-	-	128	+	+	+	+	-	-
	256	256	4	64	+	+	+	+	-	-
120	512	512	16	128	-	-	+	+	+	+
150	512	512	16	128	-	-	+	+	+	+
180	512	512	16	128	-	-	-	-	+	+
120	1024	-	-	128	-	-	+	+	+	+
150	1024	-	-	128	-	-	+	+	+	+
180	1024	-	-	128	-	-	-	-	+	+

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