A recent trend in the design of portable devices has been to use ceramic capacitors to filter DC/DC converter inputs. Ceramic capacitors are often chosen because of their small size, low equivalent series resistance (ESR) and high RMS current capability. Also, recently, designers have been looking to ceramic capacitors due to shortages of tantalum capacitors.
Unfortunately, using ceramic capacitors for input filtering can cause problems. Applying a voltage step to a ceramic capacitor causes a large current surge that stores energy in the inductances of the power leads. A large voltage spike is created when the stored energy is transferred from these inductances into the ceramic capacitor.
These voltage spikes can easily be twice the amplitude of the input voltage step.
Plug in the wall adapter at your own risk
The input voltage transient problem is related to the powerup sequence. If the wall adapter is plugged into an AC outlet and powered up first, plugging the wall adapter output into a portable device can cause input voltage transients that could damage the DC/DC converters inside the device.
Building the test circuit
To illustrate the problem, a typical 24 V wall adapter used in notebook computer applications was connected to the input of a typical notebook computer DC/DC converter. The DC/DC converter used was a synchronous buck converter that generates 3.3 V from a 24 V input.
The block diagram of the test setup is shown in Figure 1. The inductor LOUT represents the lumped equivalent inductance of the lead inductance and the output EMI filter inductor found in some wall adapters. The output capacitor in the wall adapter is usually on the order of 1000 µF; for our purposes, we can assume that it has low ESR – in the 10 mΩ to 30 mΩ range. The equivalent circuit of the wall adapter and DC/DC converter interface is actually a series resonant tank, with the dominant components being LOUT, CIN and the lumped ESR (the lumped ESR must include the ESR of CIN, the lead resistance and the resistance of LOUT).
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| Figure 1. | Block diagram of wall adapter and portable device connection. |
The input capacitor, CIN, must be a low ESR device, capable of carrying the input ripple current. In a typical notebook computer application, this capacitor is in the range of 10 µF to 100 µF. The exact capacitor value depends on a number of factors but the main requirement is that it must handle the input ripple current produced by the DC/DC converter. The input ripple current is usually in the range of 1 A to 2 A. Therefore, the required capacitors would be either one 10 µF to 22 µF ceramic capacitor, two to three 22 µF tantalum capacitors or one to two 22 µF OS-CON capacitors.
Turning on the switch
When switch SW1 in Figure 1 is turned on, the mayhem starts. Since the wall adapter is already plugged in, there is 24 V across its low impedance output capacitor. On the other hand, the input capacitor CIN is at 0 V potential. What happens from t = 0s is pretty basic. The applied input voltage will cause current to flow through LOUT. CIN will begin charging and the voltage across CIN will ramp up toward the 24 V input voltage. Once the voltage across CIN has reached the output voltage of the wall adapter, the energy stored in LOUT will raise the voltage across CIN further above 24 V. The voltage across CIN will eventually reach its peak and will then fall back to 24 V. The voltage across CIN may ring for some time around the 24 V value. The actual waveform will depend on the circuit elements.
If you intend to run this circuit simulation, keep in mind that the real-life circuit elements are very seldom linear under transient conditions. For example, the capacitors may undergo a change of capacitance (Y5V ceramic capacitors will loose 80% of the initial capacitance under rated input voltage). Also, the ESR of input capacitors will depend on the rise time of the waveform. The inductance of EMIsuppressing inductors may also drop during transients due to the saturation of the magnetic material.
Testing a portable application
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| Figure 2. | Input voltage transients across ceramic capacitors. |
Input voltage transients with typical values of CIN and LOUT used in notebook computer applications are shown in Figure 2 and Table 1. Figure 2 shows input voltage transients for CIN values of 10 µF and 22 µF with LOUT values of 1 µH and 10 µH.
| Table 1. | Peak voltages of waveforms In Figure 2 | ||||||||||||||||||||
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The top waveform shows the worst-case transient, with a 10 µF capacitor and 1 µH inductor. The voltage across CIN peaks at 57.2 V with a 24 V DC input. The DC/DC converter may not survive repeated exposure to 57.2 V.
The waveform with 10 µF and 10 µH (trace R2) looks a bit better. The peak is still around 50 V. The flat part of the waveform R2 following the peak indicates that the synchronous MOSFET M1, inside of the DC/DC converter in Figure 1, is avalanching and taking the energy hit. Traces R3 and R4 peak at around 41 V and are for a 22 µF capacitor with 1 µH and 10 µH inductors, respectively.
Input voltage transients with different input elements
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| Figure 3. | Input Transients with different input components. |
Different types of input capacitors will result in different transient voltage waveforms, as shown in Figure 3 and Table 2. The reference waveform for 22 µF capacitor and 1 µH inductor is shown in the top trace (R1); it peaks at 40.8 V.
| Table 2. | Peak voltages of waveforms In Figure 3 | ||||||||||||||||||||
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The waveform R2 in Figure 3 shows what happens when a transient voltage suppressor is added across the input. The input voltage transient is clamped but not eliminated. It is very hard to set the voltage transient’s breakdown voltage low enough to protect the DC/DC converter and far enough from the operating DC level of the input source (24 V). The transient voltage suppressor P6KE30A that was used was too close to starting to conduct at 24 V. Unfortunately, using a transient voltage suppressor with a higher voltage rating would not provide a sufficiently low clamping voltage.
The waveforms R3 and R4 are with a 22 µF, 35 V AVX TPS type tantalum capacitor and a 22 µF, 30 V Sanyo OS-CON capacitor, respectively. With these two capacitors, the transients have been brought to manageable levels. However, these capacitors are bigger than the ceramic capacitors and more than one capacitor is required in order to meet the input ripple current requirements.
Optimizing input capacitors
Waveforms in Figure 3 show how input transients vary with the type of input capacitors used.
Optimizing the input capacitors requires clear understanding of what is happening during transients. Just as in an ordinary resonant RLC circuit, the circuit in Figure 1 may have an underdamped, critically damped or overdamped transient response.
Because of the objective to minimize the size of input filter circuit, the resulting circuit is usually an underdamped resonant tank. However, a critically damped circuit is actually required. A critically damped circuit will rise nicely to the input voltage without voltage overshoots or ringing.
To keep the input filter design small, it is desirable to use ceramic capacitors because of their high ripple current ratings and low ESR. To start the design, the minimum value of the input capacitor must first be determined. In the example, it has been determined that a 22 µF, 35 V ceramic capacitor should be sufficient. The input transients generated with this capacitor are shown in the top trace of Figure 4 and in Table 3. Clearly, there will be a problem if components that are rated for 30 V are used.
| Table 3. | Peak voltages of waveforms in Figure 4 with 22 µF input ceramic capacitor and added snubber |
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To obtain optimum transient characteristic, the input circuit has to be damped. The waveform R2 shows what happens when another 22 µF ceramic capacitor with a 0.5 Ω resistor in series is added. The input voltage transient is now nicely leveled off at 30 V. Critical damping can also be achieved by adding a capacitor of a type that already has high ESR (on the order of 0.5 Ω). The waveform R3 shows the transient response when a 22 µF, 35 V TPS type tantalum capacitor from AVX is added across the input.
The waveform R4 shows the input voltage transient with a 30 V transient voltage suppressor for comparison.
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| Figure 4. | Optimizing input circuit waveforms for reduced peak voltage. |
Finally, an ideal waveform shown in Figure 4, bottom trace (Ch1) is achieved. It also turns out that this is the least expensive solution. The circuit uses a 47 µF, 35 V aluminum electrolytic capacitor from Sanyo (35CV47AXA). This capacitor has just the right value of capacitance and ESR to provide critical damping of the 22 µF ceramic capacitor in conjunction with the 1 µH of input inductance. The 35CV47AXA has an ESR value of 0.44 Ω and an RMS current rating of 230 mA. Clearly, this capacitor could not be used alone in an application with 1 A to 2 A of RMS ripple current without the 22 µF ceramic capacitor. An additional benefit is that this capacitor is very small, measuring just 6.3 mm by 6 mm.
Conclusion
Input voltage transients are a design issue that should not be ignored. Design solutions for preventing input voltage transients can be very simple and effective. If the solution is properly applied, input capacitors can be minimized and both cost and size minimized without sacrificing performance.
