12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (Cypress) - 4
| Manufacturer | Cypress |
| Description | The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2's complement output (+2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps |
| Pages / Page | 23 / 4 — Example 2. Equation 7. Equation 8. Incremental ADC. Note CAUTION: |
| File Format / Size | PDF / 394 Kb |
| Document Language | English |
Example 2. Equation 7. Equation 8. Incremental ADC. Note CAUTION:
Text Version of Document
12-Bit Incremental ADC
Example 2
For a Vref of 1.3V, you can easily calculate the expected ADC code based on the input Voltage. This calculation is done using Equation 7:
Equation 7
For an input voltage of 1V above AGND, the code from the ADC can be expected to be 3623.38. This calculation is based on Equation 8:
Equation 8
The value calculated is an ideal value and may differ based on system noise and chips offsets.
Incremental ADC
The following digital resources are used to make the integrator function as an incremental ADC: A timer to count the proper number of integration cycles. A counter to accumulate the number of cycles that the output comparator is positive. Typically, building a 12-bit incremental ADC converter requires a 12-bit timer and a 12-bit counter. Both the timer and counter would have to be clocked at one-fourth the frequency used to clock the column clock feeding the integrator. For this implementation, the timer and the counter are clocked with the same clock used by the column clock for the integrator block. The counter is incremented by four each integration cycle where the output comparator is positive, requiring that it be able to accumulate 14 bits worth of data. The timer must also be four times longer (14 bits).
Note CAUTION:
It is imperative that when placing this module, it must be configured with the same clock for all three blocks. Failure to do so causes it to operate incorrectly. To reduce the number of resources, the lower 8 bits of the timer and counter are each implemented with one digital block and the upper bits are implemented in software. The timer is set up to generate an interrupt every 256 counts or 64 integration cycles. This defines one integrate cycle. The counter is set up to integrate 64 of these time cycles. At the end of the 64th cycle, the counter is put into reset for one cycle. The sample window is 64 time cycles and the sample time is 65 integrate cycles. Document Number: 001-13252 Rev. *H Page 4 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
Example 2
For a Vref of 1.3V, you can easily calculate the expected ADC code based on the input Voltage. This calculation is done using Equation 7:
Equation 7
For an input voltage of 1V above AGND, the code from the ADC can be expected to be 3623.38. This calculation is based on Equation 8:
Equation 8
The value calculated is an ideal value and may differ based on system noise and chips offsets.
Incremental ADC
The following digital resources are used to make the integrator function as an incremental ADC: A timer to count the proper number of integration cycles. A counter to accumulate the number of cycles that the output comparator is positive. Typically, building a 12-bit incremental ADC converter requires a 12-bit timer and a 12-bit counter. Both the timer and counter would have to be clocked at one-fourth the frequency used to clock the column clock feeding the integrator. For this implementation, the timer and the counter are clocked with the same clock used by the column clock for the integrator block. The counter is incremented by four each integration cycle where the output comparator is positive, requiring that it be able to accumulate 14 bits worth of data. The timer must also be four times longer (14 bits).
Note CAUTION:
It is imperative that when placing this module, it must be configured with the same clock for all three blocks. Failure to do so causes it to operate incorrectly. To reduce the number of resources, the lower 8 bits of the timer and counter are each implemented with one digital block and the upper bits are implemented in software. The timer is set up to generate an interrupt every 256 counts or 64 integration cycles. This defines one integrate cycle. The counter is set up to integrate 64 of these time cycles. At the end of the 64th cycle, the counter is put into reset for one cycle. The sample window is 64 time cycles and the sample time is 65 integrate cycles. Document Number: 001-13252 Rev. *H Page 4 of 23 Document Outline Features and Overview Functional Description Example 1 Example 2 Incremental ADC DC and AC Electrical Characteristics CY8C29xxx Typical Performance Placement Parameters and Resources Example 1 Example 2 Interrupt Generation Control Application Programming Interface ADCINC12_Start ADCINC12_SetPower ADCINC12_Stop ADCINC12_GetSamples ADCINC12_StopAD ADCINC12_fIsDataAvailable ADCINC12_iGetData ADCINC12_ClearFlag Sample Firmware Source Code Configuration Registers Version History
