By exploiting the rise and fall time of a signal and manipulating a dc bias voltage, you can control the duty cycle of a CML signal
| Authors | Dieter Verhulst, Xin Yin |
| Main Document | Article «Circuit distorts duty cycle for CML inputs» |
| Description | Figure 2 |
| File Format / Size | PDF / 6 Kb |
| Document Language | English |
Other Materials from the Main Document
- Article «Circuit distorts duty cycle for CML inputs»
- Figure 1. This circuit can make slight adjustments to the duty cycle you apply to a CML input
- Figure 2. By exploiting the rise and fall time of a signal and manipulating a dc bias voltage, you can control the duty cycle of a CML signal
