A true op-amp made from inverters

Colin Weltin-Wu

EDN

Ever-increasing demand for smaller, more efficient CPUs has driven CMOS fabrication deep into the nanometer scale. The supply scaling and device leakage of these fine processes adversely affects precision analog circuits, leading researchers to find highly-digital alternative architectures for traditionally analog-intensive functions [1, 2]. This “digitization” of the analog domain will eventually trickle down to the home hobbyist, who will face increasing difficulty finding simple analog components. This frightening trend was foreshadowed in 1973 by a Fairchild Semiconductor application note [3]; however, none of the examples given for op-amp-like circuits provide differential inputs. This Design Idea attempts to fill this void, demonstrating a two-stage op-amp with true differential inputs and near rail-rail output swing, operating from a single 5 V supply.

Figure 1 shows the complete implementation of a two-stage op-amp using only four CD4049UBE [4] hex inverters, a resistor, and a capacitor. Note that pin 8 of U2 (Gnd) is left floating, while pin 1 of U3 (VCC) is left floating. The output of the parallel inverters in U2 is connected to the VCC pin of U1, while the output of the inverter in U3 is connected to the Gnd pin of U1.

Figure 1.

Figure 2 shows the functional transistor-level schematic of the resulting circuit, with extraneous transistors removed. The first stage is a circuit taken from [5], and implements the differential-to-single-ended conversion. The PMOS devices from the inverters in U2 behave as current sources, while NMOS in the inverter from U3 is a current sink. Unequal numbers of sources and sinks were used to pull the common mode range near mid-scale, due to the unequal NMOS and PMOS strengths.

Figure 2.

The inverters in U1 behave as a gm-doubled differential pair. Since the first stage only has between 25dB & 30dB of gain, a second stage is added. Standard compensation techniques are used to ensure overall stability, since both stages by themselves have similar bandwidths. Note that any reasonable feedback configuration forces the second stage into its linear range, obviating the need for a gain-reducing local shunt resistor.

Figure 3.	The measured gain magnitude response of the open-loop amplifier.

Table 1 A brief summary of the op-amp specifications, as prototyped. Although it has differential inputs, it does not have great common mode rejection. On the other hand, it has a larger gain-bandwidth than the classic LM741.

Figure 4.	The large-signal step response for a voltage buffer configuration, which shows some overshoot characteristic of imperfect zero cancellation.

Figure 5.	Almost true rail-to-rail operation from a single 5 V supply (the op-amp configured with a non-inverting gain of 11).

This design should work equally well with CD4069UB as well as 74HCU04 devices, although the ratio of devices in U2 and U3 may change to re-center the common-mode range with different drive strength transistors. The only critical aspect is that the inverters are unbuffered, otherwise each gain stage becomes a three-stage ring oscillator.

Figure 6.	The prototype, built on perfboard.

References:

1. Taylor, G., and I. Galton, "A reconfigurable mostly-digital ADC with a worst-case FOM of 160 dB", Symp. VLSI Circuits Dig. 2012.
2. Murmann, Boris, and Bernhard E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", Solid-State Circuits, IEEE Journal of 38.12 (2003): 2040-2050.
3. Fairchild Semiconductor, Appl. Note 88, “CMOS Linear Applications”, Jul. 1973 [revised Apr. 2003].
4. Texas Instruments, "CMOS Hex Buffer/Converter, CD4049UB/CD4050B datasheet", Aug. 1998 [revised May 2004].
5. Bazes, Mel, "Two novel fully complementary self-biased CMOS differential amplifiers" Solid-State Circuits, IEEE Journal of 26.2 (1991): 165-168.