Ilija Uzelac
EDN
This Design Idea presents a simple, proven, reliable, and robust method for charging large capacitor banks, using a series connection of power MOSFETs to raise the breakdown voltage over that of an individual MOSFET.
When a power supply drives a large capacitive load, inrush current, if not limited, can reach tens or hundreds of amps for a high voltage power supply. In general, maximal ratings of a power supply could be transiently exceeded by many times, but this is generally acceptable when the transient lasts a few AC-line cycles. This is typical for load capacitances up to a couple of hundred microfarads, but for load capacitances in thousands of microfarads, an inrush current limiter is a must.
Using MOSFETs as voltage controlled current elements is very suitable to capacitor-charging circuit design. Consider though: If a task specifies charging a capacitor bank with 1 A from rectified AC mains of 240 V, a design with a single P-MOSFET would require that at power-on, the MOSFET pass 1 A when its drain-to-source voltage |VDS| is about 330 V, which exceeds the safe operating area of most parts. For example, the IXTQ10P50P, at the maximum junction temperature of 150 °C, can handle 200 mA when |VDS| = 250 V, but over 2 A when |VDS| < 100 V. This limitation can be overcome by connecting multiple P-MOSFETs in series.
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| Figure 1. |
Figure 1 shows a design with three P-MOSFETs connected in series. Neglecting the voltage drop across R1, the input voltage is approximately the same as the potential at Q2’s source. Then, the gate potential of Q2 equals the input voltage minus 6.2 V across Zener D1, and plus any voltage drop across resistor R3. Resistors R5, R6, and R7 as voltage dividers ensure that the |VDS| of each P-MOSFET is approximately equal – about 1/3 of the voltage difference between the input and output. R5 is purposely chosen to have a slightly higher resistance than R6 and R7 as the gate potential of Q2 is about 5 V less than the input voltage. This correction equalizes |VDS| voltages even more than if resistors R5, R6, and R7 were equal. R4 ensures that at power-on/off, Q2 is turned off.
At power-on, D1 provides 6.2 V between the source and gate of Q2, |VGS2|; therefore Q2 is conductive. Q3 and Q4 are conductive as well, as the current through R5-R7 charges their gate-to-source capacitances. The capacitor bank charging current is sensed with R1 and regulated with the negative feedback control consisting of R1, Q1, R3, and Q2. When the voltage between the emitter and base of Q1 reaches VBE(on) – that is, when the charging current is about 1 A – Q1 starts to conduct. As |VGS2| = 6.2 – R3 × IC(Q1), any increase in IC(Q1) decreases |VGS2|. This decreases the output current, which in turn decreases the voltage across R1, completing the negative feedback loop.
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| Figure 2. |
Figure 2 shows voltage across the 40,000 µF capacitor bank as a function of time as the capacitor bank is charged from 0 V to 300 V – for two different cases – with and without C1. Without C1, the capacitor bank is only partially charged during each rectified half-cycle – that is, when the input voltage is higher than the output voltage plus the voltage drop across all three MOSFETs of about 15 V. Hence, the slope of the curve is not constant.
Adding C1 lets the charging circuit work with a more constant input voltage.
Calculations for C1
C1 discharges at the rate of dV/dt = I/C = 10 V/ms. This is almost order of magnitude slower than the sinusoidal change of the input voltage from 330 V to 0 V that lasts 4.17 ms for 120 Hz half-cycles. Therefore, from the moment the input voltage reaches its maximum, the capacitor bank is charged only from the C1 capacitor until the input voltage exceeds the C1 voltage on the next rising slope of the 120 Hz period. As C1 is discharged with the constant current of 1 A, the discharge time interval tD is expressed as:
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(1) |
For this time interval, the input voltage changes from 330 V to 0 V and up to VC1:
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(2) |
Solving these two equations for VC1 shows that C1 discharges down to about 265 V. As the voltage drop across three MOSFETs is about 15 V, it follows that above 250 V, the voltage across the capacitor bank doesn't increase linearly. This explains the variation from the linear dashed line in Figure 2.
This circuit is part of a complex device: our custom-built defibrillator for research studies [1]. It has proven to work reliably for hundreds of cycles and hundreds of hours with numerous rapid discharges of the capacitor bank over the last two years. The circuit is tested up to an input voltage of 280 VRMS and works reliably with a heatsink temperature of up to 70 °C. This Design Idea is not limited to the input voltage and current specified herein. The maximum input voltage and charging current can be raised with the addition of more P-MOSFETs in series. The downside is the voltage drop across each P-MOSFET of about 5 V. Larger C1 capacitances than 100 µF would linearize the charging curve at even higher voltages, or, of course, a DC input could be used.
References:
- Uzelac I, Holcomb M, Reiserer RS, Fenton FH, Wikswo JP, High-Power Current Source with Real-Time Arbitrary Waveform for In Vivo and In Vitro Studies of Defibrillation, Computing in Cardiology, 40:667-670, 2013
