Besides its mind-boggling simplicity and programmable resolution, the chief attribute of the Shannon decoder DAC (SD) is speed (Ref. 1), converting a serial n-bit digital stream into an analog signal in just nT seconds where T = 1 bit time.
Of course, whether “nT” is really fast really depends on how long T really is! Figure 1 presents an SD design in which T = 500 ms (!), making an 8 bit conversion require nT = 8 × 0.5 = 4 seconds! In what conceivable context could such a glacial pace ever qualify as “fast?”
Figure 1’s SD requires a half second to convert each bit because it relies on electromechanical relays for switching, the archaic technology being attractive because this SD has a 300-volt full scale output. There are of course ways to implement solid state (i.e., fast) switching solutions that can also handle such voltages, but relays have a charming and robust simplicity that seems a better fit to the SD KISS mystique. Here’s how it works.
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| Figure 1. | The 300 volt, 4 second, Shannon decoder DAC. |
Operating time specs for the relays (“CIT Relay and Switch” type J104D2C5VDC 15S) show 6 ms/4 ms operate/release. The resulting 6 – 4 = 2 ms ON/OFF asymmetry dictates a minimum
for 8 bit precision. The incoming 5 V bitstream on the µC output bit, O1, drives Q1 and thereby RLY1, transforming it to a 300 V bitstream.
RLY2 directs this to one of two integrating capacitors (C0 or C1) via R1 for a Shannon style time constant of
or
as shown in Figure 2, while the other integrator capacitor holds the previous conversion result for output. As each conversion reaches completion, bit O2 causes RLY2 to change state and alternate the roles of C0 and C1. For the example bit stream shown, the conversion result is
The actual T value is specific to each integrator capacitor. More on this later.
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| Figure 2. | Conversion and sample-and-hold operating sequence. |
That seems simple enough, but what’s it good for? Here’s the backstory. Several years ago, I published a Design Idea (Ref. 2) for an optically isolated ionization pulse detector amplifier.
However, the reason why the circuit needed optical isolation in the first place was only mentioned in passing. The reason was because the source of the pico-coulomb charge pulses it detected are space charge clouds of ions created by the decay of Radon atoms in air held in an ionization chamber. A voltage differential of hundreds of volts is needed to collect these ions and produce a detectable pulse. Figure 1’s circuit would allow that differential to be programmable and thus optimized for temperature, humidity, chamber dimensions, etc.
Pulse counting in the context of Radon assay is an inherently slow process involving accumulation intervals of minutes or hours, making a 4 second DAC conversion speed more than “fast” enough and hence confirms the adequacy of Figure 1’s 500 ms relay “speed”. Similar applications where a programmable electrostatic potential is needed can also be accommodated with this circuit.
But what about conversion resolution, linearity, and accuracy? Shannon decoding depends on the accuracy of conversion timing relative to T, as shown in Figure 3, showing the effect of 10% RC value error producing a ~2% = 5 LSB conversion error.
This is clearly not compatible with true 8 bit (let alone higher) SD precision.
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| Figure 3. | The effect of a 10% T = RC error producing a ~2% = 5 LSB conversion error. |
This is an important issue because, while precision resistors are inexpensive and readily available commodity components, this is unfortunately not true of precision high-voltage capacitors. C0 and C1, for example, are likely to be metalized polyester film types, available in ±10% or ±20% tolerances with tempcos of 400 to 600 ppm/°C.
So. How do we make do with cheap caps?
Accommodation of and compensation for inexpensive capacitor tolerances is the purpose of the R7-R10 resistor network, comparator U1b, and the I1 input bit. These are made use of in the time constant autocalibration sequence illustrated in Figure 4.
Autocalibration, which is performed separately for C0 and C1, begins with selection of the capacitor to be calibrated by the suitable setting of O2, followed by complete discharge of the selected capacitor by setting O1 = 0 for at least 4 seconds. O1 is then set to 1.
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| Figure 4. | Tx autocalibration sequence to compensate for large tolerances found with inexpensive capacitors. |
The selected capacitor (C1 for O1 = 0, C0 for O1 = 1) then begins to charge, generating a current pulse into the R7-R10 resistor network, which is coupled as a 5 V voltage pulse into pin 6 of U1b, driving I1 = 0. This state persists until the pin 6 pulse decays by ½ to 2.5 V (U1b pin 7 reference provided by the R5-R6 voltage divider), with pulse duration captured by the µC timing software as the appropriate timing constant, T0 or T1, and used in subsequent SD conversions.
Which leaves only the +300 V power supply circuit left to describe.
Incoming 120 VAC is isolated by a venerable Triad N-48X feeding floating full-wave rectifying voltage doubler D1, D2, C4, and C5. The 500 V pMOSFET Q2 operates as a series pass device to maintain a constant +300 V output by subtracting off excess doubler voltage under the control of level shifter Q4, op amp U1a, reference U2, and the R5-R6 voltage divider.
C3 provides stability-promoting loop bandwidth limiting.
References
- Woodward, Stephen. "The Shannon decoder: A (much) faster alternative to the PWM DAC."
- Woodward, Stephen. "FemtoAmp offers extreme gain range & isolation."
