Datasheet Actel A54SX08-2PL84

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Detailed Description

• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Setup
• 0.25 ns Clock Skew
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1,080 Flip-Flops
• 0.35 µ CMOS
• 66 MHz PCI
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft

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Other Names:

A54SX082PL84, A54SX08 2PL84