Datasheet Cypress CY8C24223-24PVIT

CY8C24123, CY8C24223, CY8C24423 PSoCTM Mixed Signal Array Preliminary Data Sheet For Silicon Revision A December 22, 2003 Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: 800.669.0557 FAX: 425.787.4641 http://www.cypress.com Document No. 38-12011 Rev. *E CY8C24xxx Preliminary Data Sheet © Cypress MicroSystems, Inc. 2000 -2003. All rights reserved. PSoCTM (Programmable System-on-ChipTM) is a trademark of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems' products in life-support system applications implies that the manufacturer assumes all risk of such use and in doing so, indemnifies Cypress MicroSystems against all charges. 2 Document No. 38-12011 Rev. *E December 22, 2003 Contents SECTION A OVERVIEW 13 Features .13 Getting Started .14 Development Kits .14 Tele-Training .14 Consultants .14 Technical Support .14 Application Notes .14 Top-Level Architecture .15 Development Tools .16 PSoC Designer Software Subsystems .16 Hardware Tools .17 User Modules and Development Process .17 Ordering Information .19 Organization and Conventions .20 Document Organization .20 Document Conventions .20 1. Pin Information .23
1.1 1.2 Pin Summary .23 Pinouts .24 Packaging Dimensions.27 Thermal Impedances .32 2. Packaging Information .27
2.1 2.2 SECTION B CORE ARCHITECTURE 33 Top-Level Core Architecture .33 Core Register Summary .34 3. CPU Core (M8C) .37
3.1 3.2 3.3 3.4 Internal Registers .37 Address Spaces .37 Instruction Set Summary.39 Instruction Format .40 3.4.1 One-Byte Instructions.40 3.4.2 Two-Byte Instructions.40 3.4.3 Three-Byte Instructions .41 Addressing Modes .41 3.5.1 Source Immediate .41 3.5.2 Source Direct .42 3.5.3 Source Indexed .42 3.5.4 Destination Direct.42 3.5 December 22, 2003 Document No. 38-12011 Rev. *E 3 Contents CY8C24xxx Preliminary Data Sheet 3.6 3.5.5 Destination Indexed .43 3.5.6 Destination Direct Source Immediate .43 3.5.7 Destination Indexed Source Immediate .43 3.5.8 Destination Direct Source Direct.44 3.5. …