Fixed-Point Digital Signal Processor 256-BGA 0 to 0
PDF, 51 Kb, File published: Apr 28, 2003
This document describes migration from the TMS320C6211 to the TMS320C6211B. The objective of this document is to indicate differences between the two devices and show how handle these differences. Depending on the board layout and any system level timing assumptions, a migration may or may not require any changes. If changes are required, some systems may be able to implement any necessary timing
PDF, 155 Kb, Revision: H, File published: Nov 10, 2005
This document describes issues of interest related to migration from the Texas Instruments TMS320C6211B/C6711/C6711B GFN package and TMS320C6711C GDP package to the TMS320C6711D digital signal processor (DSP) GDP package. The objective of this document is to indicate differences between these devices. Functions that are identical between these devices are not included. For detailed information on
PDF, 155 Kb, Revision: H, File published: Nov 11, 2005
This document describes issues of interest related to migration from the Texas Instruments TMS320C6211B/C6711/C6711B GFN package and TMS320C6713 GDP package to the TMS320C6713B digital signal processor (DSP) GDP package. The objective of this document is to indicate differences between these devices. Functions that are identical between these devices are not included. For detailed information on t
PDF, 114 Kb, Revision: C, File published: Jul 30, 2002
This document discusses the power consumption of the Texas Instruments TMS320C6201B, TMS320C6701, TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204, TMS320C6205, TMS320C6211, and TMS320C6711 digital signal processors (DSPs) for typical applications. The C6201B, C6701, C6202, C6211, and C6711 DSPs are manufactured on TI's advanced 0.18-micron process and operate with a core voltage of 1.8 V. The
PDF, 269 Kb, File published: Mar 5, 2004
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, and schedule system traffic to produce efficient designs. An example audio/video system is presented and analyzed in full. Finally, EDMA performan
