Datasheet Texas Instruments TMS320DM642AGDKA5

Manufacturer	Texas Instruments
Series	TMS320DM642
Part Number	TMS320DM642AGDKA5

Datasheets

Prices

Status

Packaging

Eco Plan

Design Kits & Evaluation Modules

• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
  XDS560v2 System Trace USB & Ethernet Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU200-U
  XDS200 USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: XDS560TRACE
  XDS560 Trace Emulator
  Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  
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• Development Kits: TMDSEVM642
  DM642 Evaluation Module
  Lifecycle Status: NRND (Not recommended for new designs)
  
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• Development Kits: TMDXDMK642
  DM64x Digital Media Developer's Kit with NTSC Camera
  Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  
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• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
  XDS560v2 System Trace USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  

Application Notes

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  Audio Echo on the DM642 EVM
  PDF, 238 Kb, File published: Aug 31, 2003
  The software demonstrates an audio loopback example on the DM642 EVM, with programmable echo added to the input signal. The demonstration creates and primes the audio I/O streams, initializes the echo buffer, enters a loop reading audio samples, then processes the samples and writes them back into the audio codec.The demonstration:Computes the read pointer and adds a sample on each
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  The TMS320DM642 Video Port Mini-Driver (Rev. A)
  PDF, 358 Kb, Revision: A, File published: Aug 14, 2003
  This application report describes the usage and design of the video capture and display mini-drivers that work on the TMS320DM642 Evaluation board (EVM). These device drivers are compliant with the DSP/BIOSв„ў IOM device driver model. The DSP?s EDMA is used to transfer data between memory and the TMS320DM642 Video Port. To maximize code reuse and streamline the integration process, both driver
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  MPEG-2 Loop Back on the DM642 EVM
  PDF, 244 Kb, File published: Aug 31, 2003
  The software demonstrates the D1 MPEG-2 encoder and decoder running back-to-back on a DM642 Evaluation Module (EVM). The demonstration encodes the captured frames and then decodes the generated MPEG-2 bitstream to display the decoded frames.The demonstration uses:MPEG-2 encoder library optimized for a DM642 EVMMPEG-2 decoder library optimized for a DM642 EVMMPEG-2 encoder and
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  JPEG Netcam2 on the DM642 EVM (Rev. A)
  PDF, 157 Kb, Revision: A, File published: Jul 16, 2004
  This software demonstration combines real-time D1 Joint Photographic Experts Group (JPEG) encoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Performing JPEG at the rate of 30 frames per second in isolation as individual images is known as motion JPEG (MJPEG). This demonstration uses:JPE
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  Driver Examples on the DM642 EVM (Rev. A)
  PDF, 1.4 Mb, Revision: A, File published: Aug 31, 2004
  The video driver example suite has twelve examples that illustrate the use of the video driver on the DM642 Evaluation Module (EVM). The examples cover all supported video capture- and display formats, and are grouped in seven project categories:NTSC capture and displayPAL capture and display16-bit RGB565 VGA display and NTSC/PAL capture8-bit grayscale VGA display and NTSC/P
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  Adapting the SPRA904 Motion Detection Application Report to the DM642 EVM
  PDF, 104 Kb, File published: Oct 10, 2003
  This application report describes the modifications that needed to be made to the multichannel motion detection system described in application report, A Multichannel Motion Detection System Using eXpressDSP RF5 NVDK Adaptation (literature number SPRA904) to port it to the DM642 EVM system.
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  An Audio Example Using Reference Frameworks on the DM642 EVM
  PDF, 222 Kb, File published: Aug 31, 2003
  The software implements audio examples for Reference Frameworks 3 and Reference Frameworks 5 on the DM642 EVM. These examples are direct ports of the Reference Frameworks examples for the TEB6415 in subdirectories apps/rf3/teb6415 and apps/rf5/projects/teb6415 under the Reference Frameworks installation.
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  Video Scaling Example on the DM642 EVM
  PDF, 250 Kb, File published: Sep 27, 2004
  The video scaling example demonstrates the real time video rescaling on DM642 EVM.The input video frames are scaled in different sizes and displayed on a VGA monitor.
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  JPEG Motion on the DM642 EVM (Rev. A)
  PDF, 168 Kb, Revision: A, File published: Jul 16, 2004
  This software demonstration combines realв€’time D1 Joint Photographic Experts Group (JPEG) encoding and decoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Performing JPEG compression at the rate of 30 frames per second in isolation as individual images is known as motion JPEG (MJPEG). This demon
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  A DSP/BIOS AIC23 Codec Device Driver for the TMS320DM642 EVM
  PDF, 80 Kb, File published: Jun 30, 2003
  This document describes the usage and design of a device driver for the AIC23 audio codec on the TMS320DM642 EVM. This device driver is written in conformance to the DSP/BIOSв„ў IOM device driver model and uses the generic TMS320C6x1x EDMA McASP driver to transfer samples to and from the serial port. For details on this generic driver, see the application note A DSP/BIOS EDMA McASP Device D
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  JPEG Netcam on the DM642 EVM (Rev. A)
  PDF, 154 Kb, Revision: A, File published: Jul 16, 2004
  This software demonstration combines real-time D1 Joint Photographic Experts Group (JPEG) encoding and decoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Performing JPEG compression at the rate of 30 frames per second in isolation as individual images is known as motion JPEG (MJPEG). This demonstrat
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  On-Screen-Display Driver Examples For DM642 EVM Demo Software Release Report
  PDF, 109 Kb, File published: Oct 14, 2003
  The On-Screen-Display (OSD) driver examples illustrate the usage of the OSD driver on the DM642 EVM. The examples also cover all display formats supported by the OSD FPGA of the DM642 EVM.
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  JPEG Loop Back on the DM642 EVM
  PDF, 216 Kb, File published: Aug 31, 2003
  The software demonstrates real-time D1 JPEG encoding and decoding of images on a DM642 EVM. The JPEG standard pertains to compression of still images. Performing JPEG at the rate of 30 frames per second, in isolation, as individual images, is considered motion JPEG (MJPEG). The demonstration uses:JPEG encoder library optimized for a DM642 EVM capable of real-time D1 encodingJPEG dec
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  Interfacing a CMOS Sensor to the TMS320DM642 Using Raw Capture Mode (Rev. A)
  PDF, 654 Kb, Revision: A, File published: Jan 27, 2010
  This document contains information on how to interface the TMS320DM642 to a CMOS Digital Image Sensor in raw capture mode. A complete example is shown, including hardware and software interfaces. The software consists of a set of routines that are compatible with the Video Port Mini-Driver and External Device Control interface. The discussed interface is proven and has been tested from 320x240 at
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  Audio Demonstration on the DM642 EVM
  PDF, 220 Kb, File published: Aug 31, 2003
  The software demonstrates a g.729a voice codec running on the DM642 EVM. The demonstration collects stereo samples and plays back the resulting samples. The right channel samples are not modified and fed straight through. The left channel samples are fed through a g.729a encoding and decoding process and the resulting samples are played back.The demonstration uses/features:Low pass
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  TMS320DM642 Hardware Designer's Resource Guide (Rev. A)
  PDF, 197 Kb, Revision: A, File published: Oct 25, 2005
  The DSP Hardware Designer's Resource Guide is organized by development flow and functional areas to make your design effort as seamless as possible. Topics covered include getting started, board design, system testing, and checklists to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, models, symbols, and refere
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  MPEG-2 Encoder on the DM642 EVM
  PDF, 230 Kb, File published: Aug 31, 2003
  The software demonstrates real-time D1 MPEG-2 encoding on the DM642 EVM. The demonstration encodes the captured frames and displays all the frames from the reconstruction loop of the encoder.The demonstration uses:MPEG-2 encoder library optimized for DM642 EVM capable of real-time D1 encodingMPEG-2 encoder library implemented using XDAIS interfacesSample integration of the MP
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  TMS320DM642 EVM Daughtercard Specification Revision 1.0
  PDF, 191 Kb, File published: Jun 25, 2003
  The daughtercard specification is based on the interface provided with the TMS320DM642 (DM642) Evaluation Module (EVM). This specification provides the information ecessary to allow daughtercards to be designed to function with the DM642 EVM. It also provides guidelines for designing new DSP motherboards aiming to provide a compatible interface. This includes systems based on different DSPs as we
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  MPEG-2 High Definition Decoder on the DM642 EVM
  PDF, 717 Kb, File published: Aug 31, 2003
  The software demonstrates the MPEG-2 high-definition (HD) decoder running on the DM642 Evaluation Module (EVM). The demonstration uses the MPEG-2 HD decoder to decode the MPEG-2 HD bitstream and display the decoded frames on the HD output device.The demonstration uses:MPEG-2 decoder library optimized for a DM642 EVMMPEG-2 decoder library implemented using XDAIS interfacesSamp
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  JPEG Network on the DM642 EVM (Rev. A)
  PDF, 168 Kb, Revision: A, File published: Jul 16, 2004
  This software demonstration combines real-time D1 Joint Photographic Experts Group (JPEG) encoding of images on the DM642 Evaluation Module (EVM) with networking functionality.The JPEG standard pertains to compression of still images. Performing JPEG at the rate of 30 frames per second in isolation as individual images is known as motion JPEG (MJPEG). This demonstration uses:JPEG
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  H.263 Loop Back on the DM642 EVM
  PDF, 209 Kb, File published: Aug 31, 2003
  The software demonstrates the D1 H263 encoder and decoder on the DM642 Evaluation Module (EVM). The demonstration encodes the captured frames and then decodes the generated H263 bit-steam to display the decoded frames.The demonstration uses:H263 encoder library optimized for a DM642 EVMH263 decoder library optimized for a DM642 EVMH263 encoder and decoder library implemented
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  Interfacing an LCD Controller to a DM642 Video Port (Rev. B)
  PDF, 263 Kb, Revision: B, File published: May 3, 2004
  There is an increasing demand to bring video and image processing capabilities to devices like video IP phones, cellular phones, and personal data assistants (PDAs). The images are brought to the user on liquid crystal displays that usually use thin film transistor (TFT) technology. These LCD devices require very specific timings and row/column formatting that can make them difficult to directly i
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  High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A)
  PDF, 440 Kb, Revision: A, File published: May 3, 2004
  The DM642 DSP has three 20-bit video ports capable of high definition (HD) display. The video ports can be programmed to follow HDTV standards, such as SMPTE274M and SMPTE296M. These HDTV standards follow a 4:2:2 convention where luminance and chrominance signals are separated onto two different 8- or 10-bit data paths. This convention is more commonly called Y/C mode. Many new HD displays accept
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  TMS320DM64x Power Consumption Summary (Rev. F)
  PDF, 60 Kb, Revision: F, File published: Feb 18, 2005
  This document discusses the power consumption of the Texas Instruments TMS320DM640, TMS320DM641, TMS320DM642, and TMS320DM643 digital signal processors (DSPs). Power consumption on these devices is highly application-dependent, so a spreadsheet is provided to model power consumption for a user's application. To get good results from the spreadsheet, realistic usage parametersmust be entered. T
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  TMS320DM642 to TMS320DM6437 Migration Guide
  PDF, 141 Kb, File published: Jun 29, 2007
  This document describes device considerations for migrating a design based on a TI TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor (DSP) to one based on a TI TMS320DM6437 Digital Media Processor (DMP). These two devices are based on similar DSP CPU cores, and feature video front- and back-end processing capability, and a similar mixture of memory and other peripherals useful in a sy
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  The TMS320DM642 Video Port Mini-Driver for TVP5146 and TVP5150 decoder
  PDF, 57 Kb, File published: Jul 16, 2004
  This application report describes the usage and design of the video capture miniв€’drivers that work on the TMS320DM642 Evaluation Module (EVM) with TVP5146 and TVP5150A decoders. Use this application report as well as The TMS320DM642 Video Port Miniв€’Driver (spra918a) to understand the usage of the video decoder driver. These device drivers are compliant with the DSP/BIOS IOM device dri
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  TMS320DM642 to TMS320DM6467 Migration
  PDF, 241 Kb, File published: Nov 17, 2008
  This document describes device considerations to migrate a design based on a TI TMS320DM642 video/imaging fixed-point Digital Signal Processor (DSP) to one based on a TI TMS320DM6467 Digital Media System-on-Chip (DMSoC). These two devices are based on similar DSP CPU cores, feature video processing capability, and a mixture of memory and other peripherals useful in a system environment. This docum
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  Software Migration From TMS320DM642 to TMS320DM648/DM6437
  PDF, 178 Kb, File published: Aug 19, 2008
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  Migrating from TMS320DM642/3/1/0 to the TMS320DM647/DM648 Device
  PDF, 79 Kb, File published: Jun 7, 2007
  This application report describes issues of interest related to migration from the TMS320DM642/3/1/0 to the TMS320DM648/7 device. The objective of this document is to indicate differences between the two device portfolios. Functions that are identical between the two devices are not included. For detailed information on the specific functions of either device, see the TMS320DM642, TMS320DM643, or
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  Cache Usage in High-Performance DSP Applications with the TMS320C64x
  PDF, 129 Kb, File published: Dec 13, 2001
  The TMS320C64xв„ў, the newest member of the TMS320C6000в„ў (C6000в„ў) family, is used in high-performance DSP applications. The C64xв„ў processes information at a rate of 4800 MIPs, while operating at a clock rate of 600 MHz. Processing data at these extremely high rates requires fast memory that is directly connected to the CPU (Central Processing Unit). However, a bandwidth dilem
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  TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
  PDF, 248 Kb, Revision: C, File published: Apr 17, 2002
  This application report describes an interface between the Texas Instruments TMS320C6000в„ў DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between these two devices is that the PCI9052 is somewhat faster than the PCI9050.This application report includes a diagram showing connections be
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  TMS320C6000 Enhanced DMA: Example Applications (Rev. A)
  PDF, 1.4 Mb, Revision: A, File published: Oct 24, 2001
  The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA channels can be set up to operate continuously without requiring CPU intervention or reprogramming. This allows the CPU to use its
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  Use and Handling of Semiconductor Packages With ENIG Pad Finishes
  PDF, 129 Kb, File published: Aug 31, 2004
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  TMS320C6000 Host Port to MC68360 Interface (Rev. A)
  PDF, 261 Kb, Revision: A, File published: Sep 30, 2001
  This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams
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  TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
  PDF, 272 Kb, Revision: A, File published: Aug 31, 2001
  This application report describes the interface between the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing diagrams).
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  TMS320C6000 Host Port to MPC860 Interface (Rev. A)
  PDF, 311 Kb, Revision: A, File published: Jun 21, 2001
  This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing
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  TMS320C6000 System Clock Circuit Example (Rev. A)
  PDF, 129 Kb, Revision: A, File published: Aug 15, 2001
  This document describes how to provide the Texas Instruments TMS320C6000в„ў DSP with a system clock. All of the clocks internal to the C6000в„ў are generated from a single source through the CLKIN pin. This source clock for the device is an external signal that, depending on the clock mode, either drives the on-chip Phase-Locked Loop (PLL) circuit, which multiplies the source clock in freq
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  Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
  PDF, 309 Kb, Revision: A, File published: Sep 30, 2001
  This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external memory interface (EMIF) can be used to support PCI bus mastering. Details on the signals and logic required to implement both PCI slave and maste
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  TMS320C6000 McBSP: I2S Interface
  PDF, 93 Kb, File published: Sep 8, 1999
  This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a protocol for transmitting two channels of digital audio data over a single serial connection.The flexible McBSP in the TMS320C6000 supports the I
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  General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point
  PDF, 50 Kb, File published: Jan 31, 2000
  Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to handle these logarithmic and exponential operations.This application report provides a general guide to implement these operations on fixed-
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  TMS320C6000 C Compiler: C Implementation of Intrinsics
  PDF, 154 Kb, File published: Dec 7, 1999
  The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that once you have performed the first optimization step, your C source code is no longer ANSI C compatible. The code proposed within this appli
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  TMS320C6000 McBSP Initialization (Rev. C)
  PDF, 232 Kb, Revision: C, File published: Mar 8, 2004
  The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps necessary when either the (E)DMA or the CPU is used to service the McBSP data. Typically, the (E)DMA is used to perform read/write transfers from
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  Using a TMS320C6000 McBSP for Data Packing (Rev. A)
  PDF, 257 Kb, Revision: A, File published: Oct 31, 2001
  This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/from the McBSP as a single 16/24/32-bit element or multiple successive 16-bit words to/from the McBSP as a single 32-bit word.The McBSP
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  TMS320C6000 Board Design: Considerations for Debug (Rev. C)
  PDF, 96 Kb, Revision: C, File published: Apr 21, 2004
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  TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
  PDF, 284 Kb, Revision: A, File published: May 21, 2001
  This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also describes the usage of McBSP registers and sample code to perform the above function.
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  TMS320C6000 EMIF to External Flash Memory (Rev. A)
  PDF, 471 Kb, Revision: A, File published: Feb 13, 2002
  Interfacing external flash memory to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a variety of external memory devices.This document describes the following:EMIF control registers and asynchronous interface signals<
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  TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
  PDF, 289 Kb, Revision: A, File published: Jul 10, 2001
  This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec 1997 device. This application report uses the TLV320AIC27 audio codec (AIC27) as an example. The audio codec 1997 (AC'97) standard spec
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  Circular Buffering on TMS320C6000 (Rev. A)
  PDF, 172 Kb, Revision: A, File published: Sep 12, 2000
  This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) samples. Circular addressing simplifies the manipulation of pointers in accessing the data samples.This application report addresses the following
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  TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
  PDF, 240 Kb, Revision: A, File published: Jul 23, 2001
  This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processor which is a m-law companding device. The interface is also applicable to TI?s TLV320AC57, an A-law companding audio processor.The highly
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  Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
  PDF, 296 Kb, Revision: A, File published: Aug 31, 2001
  This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000в„ў DSP device can be connected to a McBSP on another C6000 DSP device to serve as a high-speed data communication port. Typically, McBSPs of similar device numbers a
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  TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
  PDF, 150 Kb, File published: Feb 2, 2000
  This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial port (McBSP) in the TMS320C6000 supports two companding formats: mu-Law and A-Law. Both companding formats are specified in the CCITT G.711
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  TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
  PDF, 185 Kb, Revision: D, File published: Apr 26, 2004
  Texas Instruments TMS320C6000в„ў digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot configuration settings at reset.The boot process performed by the DSP is to either load code from an external read-only memory (ROM) space
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  TMS320C6000 McBSP as a TDM Highway (Rev. A)
  PDF, 313 Kb, Revision: A, File published: Sep 11, 2000
  This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000в„ў digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform data transfer. Thus, multiple users operate various channels; however, each user has a set of channel(s) assigned for transmission and re
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  TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
  PDF, 87 Kb, Revision: B, File published: Jun 4, 2002
  This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the framing signal, clock, and data from the ST-BUSв„ў device and processes them to generate internal frame syncs and clocks for correct data
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  TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
  PDF, 833 Kb, Revision: E, File published: Sep 4, 2007
  Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices.This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM function
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  TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
  PDF, 118 Kb, Revision: A, File published: Aug 31, 2001
  Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TIв„ў) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The EMIF provides a glueless interface to a variety of external memory devices.This document describes:EMIF control registers and ASR
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  TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
  PDF, 99 Kb, Revision: C, File published: Jun 30, 2001
  The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order to communicate with the SPI ROM. The McBSP initialization and contr
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  TMS320C6000 Board Design for JTAG (Rev. C)
  PDF, 89 Kb, Revision: C, File published: Apr 2, 2002
  Designing a TMS320C6000в„ў DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for emulation or for boundary scan. It is therefore necessary to provide flexibility in the design to accommodate those modes that are desired.
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  Using IBIS Models for Timing Analysis (Rev. A)
  PDF, 301 Kb, Revision: A, File published: Apr 15, 2003
  Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d
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  TMS320C6000 EDMA IO Scheduling and Performance
  PDF, 269 Kb, File published: Mar 5, 2004
  The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, and schedule system traffic to produce efficient designs. An example audio/video system is presented and analyzed in full. Finally, EDMA performan
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  TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
  PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
  This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
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  Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
  PDF, 127 Kb, File published: May 20, 2007
  As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (PCB) design. This application report addresses the thermal considerations for the TMS320DM64xx, TMS320DM64x, and TMS320C6000в„ў DSP devices.
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Kb, File published: Oct 6, 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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• Semiconductors > Processors > Digital Signal Processors > Media Processors > Digital Video Processors