Datasheet Texas Instruments SN74LVTH125D

Manufacturer	Texas Instruments
Series	SN74LVTH125
Part Number	SN74LVTH125D

3.3-V ABT Quadruple Bus Buffers With 3-State Outputs 14-SOIC -40 to 85

Datasheets

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PDF, 1.1 Mb, Revision: I, File published: Oct 13, 2003

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	14
Package Type	D
Industry STD Term	SOIC
JEDEC Code	R-PDSO-G
Package QTY	50
Carrier	TUBE
Device Marking	LVTH125
Width (mm)	3.91
Length (mm)	8.65
Thickness (mm)	1.58
Pitch (mm)	1.27
Max Height (mm)	1.75
Mechanical Data	Download

Parametrics

Bits	4
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	0.007 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	-32/64 mA
Package Group	SOIC
Package Size: mm2:W x L	14SOIC: 52 mm2: 6 x 8.65(SOIC) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	3.5 ns

Eco Plan

RoHS

Compliant

Application Notes

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Simultaneous-Switching Performance of TI Logic Devices (Rev. B)
PDF, 378 Kb, Revision: B, File published: Feb 23, 2005
Simultaneous-switching noise can generate and propagate glitches in electronic systems. Therefore, system designers are faced with challenges to minimize simultaneous-switching noise, while increasing switching speed and improving signal quality. This report presents the performance of different TI logic devices under various simultaneous-switching conditions. Factors such as the number of bits sw
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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, File published: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Series: SN74LVTH125 (21)

SN74LVTH125D SN74LVTH125DBR SN74LVTH125DBRE4 SN74LVTH125DE4 SN74LVTH125DG4 SN74LVTH125DGVR SN74LVTH125DGVRE4 SN74LVTH125DGVRG4 SN74LVTH125DR SN74LVTH125DRE4 SN74LVTH125DRG4 SN74LVTH125NSR SN74LVTH125NSRE4 SN74LVTH125PW SN74LVTH125PWE4 SN74LVTH125PWG4 SN74LVTH125PWR SN74LVTH125PWRE4 SN74LVTH125PWRG4 SN74LVTH125RGYR SN74LVTH125RGYRG4

Manufacturer's Classification

Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver