Datasheet Texas Instruments TMS320C6211BGFN180
| Manufacturer | Texas Instruments |
| Series | TMS320C6211B |
| Part Number | TMS320C6211BGFN180 |
Fixed-Point Digital Signal Processor 256-BGA
Datasheets
TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors datasheet
PDF, 1.2 Mb, Revision: L, File published: Jun 9, 2004
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Prices
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 256 | 256 | 256 |
| Package Type | GFN | GFN | GFN |
| Industry STD Term | BGA | BGA | BGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N | S-PBGA-N |
| Device Marking | 180 | TMS320C6211B | GFN |
| Width (mm) | 27 | 27 | 27 |
| Length (mm) | 27 | 27 | 27 |
| Thickness (mm) | 1.72 | 1.72 | 1.72 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 2.32 | 2.32 | 2.32 |
| Mechanical Data | Download | Download | Download |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Application Notes
- Optimizing JPEG on the TMS320C6211 2-Level Cache DSPPDF, 312 Kb, File published: Sep 13, 2000
This application report describes the implementation and optimization techniques of the Joint Photographic Experts Group (JPEG), the still image compression standard on the TMS320C6211. The TMS320C6211 is a low-cost and high-performance digital signal processor (DSP) with 2-level caches, that utilizes the VelociTI? very-long-instruction-word (VLIW) architecture.The TMS320C6211 has 64KB of L2 m - TMS320C6211 to TMS320C6211B Migration GuidePDF, 51 Kb, File published: Apr 28, 2003
This document describes migration from the TMS320C6211 to the TMS320C6211B. The objective of this document is to indicate differences between the two devices and show how handle these differences. Depending on the board layout and any system level timing assumptions, a migration may or may not require any changes. If changes are required, some systems may be able to implement any necessary timing - TMS320C621x/C671x EDMA Queue Management GuidelinesPDF, 151 Kb, File published: Nov 7, 2000
The enhanced DMA (EDMA) controller of the TMS320C621x and TMS320C671x devices is a highly efficient data transfer engine, controlling all of the data movement beyond the level-two memory of the device. There are sixteen channels and a quick DMA (QDMA) available to perform programmable data transfers, giving a great deal of flexibility. With this flexibility comes the responsibility to intelligentl - Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H)PDF, 155 Kb, Revision: H, File published: Nov 10, 2005
This document describes issues of interest related to migration from the Texas Instruments TMS320C6211B/C6711/C6711B GFN package and TMS320C6711C GDP package to the TMS320C6711D digital signal processor (DSP) GDP package. The objective of this document is to indicate differences between these devices. Functions that are identical between these devices are not included. For detailed information on - Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H)PDF, 155 Kb, Revision: H, File published: Nov 11, 2005
This document describes issues of interest related to migration from the Texas Instruments TMS320C6211B/C6711/C6711B GFN package and TMS320C6713 GDP package to the TMS320C6713B digital signal processor (DSP) GDP package. The objective of this document is to indicate differences between these devices. Functions that are identical between these devices are not included. For detailed information on t - TMS320C621x/TMS320C671x EDMA ArchitecturePDF, 255 Kb, File published: Mar 5, 2004
The enhanced DMA (EDMA) controller of the TMS320C621xв„ў/TMS320C671xв„ў device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the architecture of the engine. Transfer requests (TRs) originate from many requestors, including sixteen programmable EDMA channels, the lev - TMS320C621x/671x EDMA Performance DataPDF, 233 Kb, File published: Mar 5, 2004
The enhanced DMA (EDMA) controller of the TMS320C621xв„ў/TMS320C671xв„ў devices is a highly efficient data transfer engine, capable of maintaining transfers at up to 1800 MB/sec at a 225 MHz CPU clock frequency. This document details actual bandwidth achieved under various operating conditions. Ideal transfer bandwidth is explored in TMS320C6000 EDMA IO Scheduling and Performance (S - MPEG-2 Video Decoder: TMS320C62x (TM) DSP ImplementationPDF, 80 Kb, File published: Feb 29, 2000
This application report describes the implementation of the MPEG-2 video decoder on the TMS320C62x(tm)DSP. The MPEG-2 video standard specifies the decompression and coded representation for entertainment-quality digital video, and is widely used in different digital video systems including DVB, DTV, DVD, DSS, etc. The decoder software implements all the MPEG-2 main-profile-at-main-level functional - IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B)PDF, 92 Kb, Revision: B, File published: Jan 4, 2000
This application report provides a detailed description of the implementation of the IS-12 enhanced variable rate speech codec (EVRC) on the Texas Instrument (TI)(tm) TMS320C62x digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirements, and performance evaluation. Issues on multichannel implementation and interrupts are also addressed. - G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)PDF, 74 Kb, Revision: B, File published: Jan 4, 2000
This document provides a detailed description of the implementation of the G.729 speech encoder and decoder (codec) on the Texas Instruments (TI)(tm) TMS320C6201 digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirements, and performance evaluation. Issues regarding multichannel implementation and interrupts are also addressed.Source - Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62xPDF, 177 Kb, File published: Nov 23, 2002
This paper discusses a method by which the Texas Instruments (TI)(tm) TMS320C62xx or C62xx high performance fixed point DSPs overcome the traditional advantage held by floating point DSPs -- precision and speed.Using the Radix-4 Fast Fourier Transform (FFT), this document illustrates how extended precision arithmetic, multiplication in particular, can be performed on the 'C62xx. Using the te - On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62xPDF, 219 Kb, File published: Jul 29, 1999
This application report describes the implementation of MPEG-4 motion compensation on the Texas Instruments (TI)(tm) TMS320C62x digital signal processor (DSP). MPEG-4 is a standard for coding of audiovisual information being developed by the Motion Picture Experts Group (MPEG). MPEG-4 became an International Standard in December 1998. Motion compensation is a basic component of MPEG-4 and other vi - ETSI Math Operations in C for the TMS320C62x (Rev. A)PDF, 51 Kb, Revision: A, File published: Nov 13, 2000
Many standard vocoders follow the European Telecommunications Standards Institute (ETSI) for all math operations. One of the purposes of the ETSI math functions is to standardize all math operations into a set of function calls that can be reused by many different vocoders now and in the future.The Global Systems for Mobile Communications (GSM) standard requires vocoders that follow the ETSI s - G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)PDF, 116 Kb, Revision: B, File published: Jan 4, 2000
This application report describes how the G.723.1 Dual-Rate Speech Coder has been implemented on the TMS320C62x digital signal processor (DSP). Beyond the use of the ?C62x intrinsic functions, the application report includes specific changes required to allow this coder to operate in a real-time system with other speech coders. Also reported is information on several optimization techniques used t - GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)PDF, 83 Kb, Revision: B, File published: Jan 4, 2000
This document provides a detailed description of the implementation of the GSM enhanced full rate (EFR) speech encoder and decoder (codec) on the Texas Instruments (TI)(tm)TMS320C62x digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirement, and performance evaluation. Issues on multichannel implementation and interrupts are also addresse - TMS320C6000 DMA Example Applications (Rev. A)PDF, 864 Kb, Revision: A, File published: Apr 10, 2002
The TMS320C6000? on-chip direct memory access (DMA) controller from Texas Instruments is used to transfer data between two locations in the memory map in the background of CPU operation. Typically, the DMA is used to:Transfer blocks of data between external and internal data memoriesRestructure portions of internal data memoryContinually service a peripheralPage program s - TMS320C6000 Enhanced DMA: Example Applications (Rev. A)PDF, 1.4 Mb, Revision: A, File published: Oct 24, 2001
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA channels can be set up to operate continuously without requiring CPU intervention or reprogramming. This allows the CPU to use its - TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)PDF, 248 Kb, Revision: C, File published: Apr 17, 2002
This application report describes an interface between the Texas Instruments TMS320C6000в„ў DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between these two devices is that the PCI9052 is somewhat faster than the PCI9050.This application report includes a diagram showing connections be - TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)PDF, 272 Kb, Revision: A, File published: Aug 31, 2001
This application report describes the interface between the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing diagrams). - TMS320C6000 Host Port to MPC860 Interface (Rev. A)PDF, 311 Kb, Revision: A, File published: Jun 21, 2001
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing - TMS320C6000 Host Port to MC68360 Interface (Rev. A)PDF, 261 Kb, Revision: A, File published: Sep 30, 2001
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams - General Guide to Implement Logarithmic and Exponential Operations on Fixed-PointPDF, 50 Kb, File published: Jan 31, 2000
Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to handle these logarithmic and exponential operations.This application report provides a general guide to implement these operations on fixed- - Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)PDF, 309 Kb, Revision: A, File published: Sep 30, 2001
This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external memory interface (EMIF) can be used to support PCI bus mastering. Details on the signals and logic required to implement both PCI slave and maste - TMS320C6000 System Clock Circuit Example (Rev. A)PDF, 129 Kb, Revision: A, File published: Aug 15, 2001
This document describes how to provide the Texas Instruments TMS320C6000в„ў DSP with a system clock. All of the clocks internal to the C6000в„ў are generated from a single source through the CLKIN pin. This source clock for the device is an external signal that, depending on the clock mode, either drives the on-chip Phase-Locked Loop (PLL) circuit, which multiplies the source clock in freq - TMS320C6000 McBSP: I2S InterfacePDF, 93 Kb, File published: Sep 8, 1999
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a protocol for transmitting two channels of digital audio data over a single serial connection.The flexible McBSP in the TMS320C6000 supports the I - Circular Buffering on TMS320C6000 (Rev. A)PDF, 172 Kb, Revision: A, File published: Sep 12, 2000
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) samples. Circular addressing simplifies the manipulation of pointers in accessing the data samples.This application report addresses the following - TMS320C6000 Board Design for JTAG (Rev. C)PDF, 89 Kb, Revision: C, File published: Apr 2, 2002
Designing a TMS320C6000в„ў DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for emulation or for boundary scan. It is therefore necessary to provide flexibility in the design to accommodate those modes that are desired. - TMS320C6000 McBSP: IOM-2 Interface (Rev. A)PDF, 284 Kb, Revision: A, File published: May 21, 2001
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also describes the usage of McBSP registers and sample code to perform the above function. - Using a TMS320C6000 McBSP for Data Packing (Rev. A)PDF, 257 Kb, Revision: A, File published: Oct 31, 2001
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/from the McBSP as a single 16/24/32-bit element or multiple successive 16-bit words to/from the McBSP as a single 32-bit word.The McBSP - TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)PDF, 289 Kb, Revision: A, File published: Jul 10, 2001
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec 1997 device. This application report uses the TLV320AIC27 audio codec (AIC27) as an example. The audio codec 1997 (AC'97) standard spec - TMS320C6000 McBSP Initialization (Rev. C)PDF, 232 Kb, Revision: C, File published: Mar 8, 2004
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps necessary when either the (E)DMA or the CPU is used to service the McBSP data. Typically, the (E)DMA is used to perform read/write transfers from - TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)PDF, 118 Kb, Revision: A, File published: Aug 31, 2001
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TIв„ў) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The EMIF provides a glueless interface to a variety of external memory devices.This document describes:EMIF control registers and ASR - TMS320C6000 EMIF to External Flash Memory (Rev. A)PDF, 471 Kb, Revision: A, File published: Feb 13, 2002
Interfacing external flash memory to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a variety of external memory devices.This document describes the following:EMIF control registers and asynchronous interface signals< - TMS320C6000 C Compiler: C Implementation of IntrinsicsPDF, 154 Kb, File published: Dec 7, 1999
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that once you have performed the first optimization step, your C source code is no longer ANSI C compatible. The code proposed within this appli - TMS320C6000 Board Design: Considerations for Debug (Rev. C)PDF, 96 Kb, Revision: C, File published: Apr 21, 2004
- TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)PDF, 99 Kb, Revision: C, File published: Jun 30, 2001
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order to communicate with the SPI ROM. The McBSP initialization and contr - TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)PDF, 833 Kb, Revision: E, File published: Sep 4, 2007
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices.This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM function - TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)PDF, 185 Kb, Revision: D, File published: Apr 26, 2004
Texas Instruments TMS320C6000в„ў digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot configuration settings at reset.The boot process performed by the DSP is to either load code from an external read-only memory (ROM) space - TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)PDF, 240 Kb, Revision: A, File published: Jul 23, 2001
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processor which is a m-law companding device. The interface is also applicable to TI?s TLV320AC57, an A-law companding audio processor.The highly - Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)PDF, 296 Kb, Revision: A, File published: Aug 31, 2001
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000в„ў DSP device can be connected to a McBSP on another C6000 DSP device to serve as a high-speed data communication port. Typically, McBSPs of similar device numbers a - TMS320C6000 u-Law and a-Law Companding with Software or the McBSPPDF, 150 Kb, File published: Feb 2, 2000
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial port (McBSP) in the TMS320C6000 supports two companding formats: mu-Law and A-Law. Both companding formats are specified in the CCITT G.711 - TMS320C6000 McBSP as a TDM Highway (Rev. A)PDF, 313 Kb, Revision: A, File published: Sep 11, 2000
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000в„ў digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform data transfer. Thus, multiple users operate various channels; however, each user has a set of channel(s) assigned for transmission and re - TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)PDF, 87 Kb, Revision: B, File published: Jun 4, 2002
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the framing signal, clock, and data from the ST-BUSв„ў device and processes them to generate internal frame syncs and clocks for correct data - Using IBIS Models for Timing Analysis (Rev. A)PDF, 301 Kb, Revision: A, File published: Apr 15, 2003
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d - Thermal Considerations for the DM64xx, DM64x, and C6000 DevicesPDF, 127 Kb, File published: May 20, 2007
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (PCB) design. This application report addresses the thermal considerations for the TMS320DM64xx, TMS320DM64x, and TMS320C6000в„ў DSP devices.
Model Line
Series: TMS320C6211B (12)
Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP
