Datasheet Texas Instruments TMS320C6670XCPY2
| Manufacturer | Texas Instruments |
| Series | TMS320C6670 |
| Part Number | TMS320C6670XCPY2 |
Multicore Fixed and Floating-Point System-on-Chip 841-FCBGA 0 to 85
Datasheets
TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip datasheet
PDF, 2.4 Mb, Revision: D, File published: Mar 7, 2012
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 841 |
| Package Type | CYP |
| Width (mm) | 24 |
| Length (mm) | 24 |
| Thickness (mm) | 2.82 |
| Mechanical Data | Download |
Parametrics
| Applications | Communications and Telecom |
| Approx. Price (US$) | 168.00 | 1ku |
| DRAM | DDR3 |
| DSP | 4 C66x |
| DSP MHz (Max.) | 1000 1200 |
| EMAC | 10/100/1000 |
| GFLOPS | 64 76.8 |
| Hardware Accelerators | VCP2 TCP3d TCP3e FFT Coprocessor |
| On-Chip L2 Cache | 4096 KB |
| Operating Temperature Range(C) | -40 to 100 0 to 85 |
| Other On-Chip Memory | 2048 KB |
| PCI/PCIe | 2 PCIe Gen2 |
| Package Size: mm2:W x L (PKG) | See datasheet (FCBGA) |
| Rating | Catalog |
| Serial I/O | AIF2 I2C RapidIO SPI UART |
| Serial RapidIO | 1 (four lanes) |
| Total On-Chip Memory (KB) | 6528 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Design Kits & Evaluation Modules
- Development Kits: TMDSEVM6670
TMS320C6670 Evaluation Modules
Lifecycle Status: Active (Recommended for new designs) - Development Kits: TMDSEVM6678
TMS320C6678 Evaluation Modules
Lifecycle Status: Active (Recommended for new designs) - Daughter Cards: TMDXEVMPCI
AMC to PCIe Adapter Card
Lifecycle Status: Active (Recommended for new designs) - Development Kits: HL5CABLE
Hyperlink Cable
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone DevicesPDF, 640 Kb, File published: Nov 9, 2010
- Connecting AIF to FFTC Guide for KeyStone DevicesPDF, 441 Kb, File published: Nov 9, 2010
- Keystone NDK FAQPDF, 54 Kb, File published: Oct 3, 2016
This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices. - TI Keystone DSP Hyperlink SerDes IBIS-AMI ModelsPDF, 3.2 Mb, File published: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface. - TI Keystone DSP PCIe SerDes IBIS-AMI ModelsPDF, 4.8 Mb, File published: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface. - SerDes Implementation Guidelines for KeyStone I DevicesPDF, 590 Kb, File published: Oct 31, 2012
The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge - KeyStone I DDR3 Initialization (Rev. E)PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP - TMS320C66x DSP Generation of Devices (Rev. A)PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
- Hardware Design Guide for KeyStone Devices (Rev. C)PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
- Tuning VCP2 and TCP2 Bit Error Rate PerformancePDF, 293 Kb, File published: Feb 11, 2011
In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, File published: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, File published: Dec 13, 2011The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROMOptimizing Loops on the C66x DSPPDF, 585 Kb, File published: Nov 9, 2010Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, File published: Nov 9, 2010DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, File published: Jun 5, 2014Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicoreThermal Design Guide for DSP and ARM Application Processors (Rev. A)PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal requireModel Line
Series: TMS320C6670 (17)Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP
