Datasheet Texas Instruments TMS320C6654CZH8
| Manufacturer | Texas Instruments |
| Series | TMS320C6654 |
| Part Number | TMS320C6654CZH8 |
Fixed and Floating Point Digital Signal Processor 625-FCBGA 0 to 85
Datasheets
TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 1.7 Mb, Revision: D, File published: Jun 22, 2016
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 625 | 625 | 625 |
| Package Type | CZH | CZH | CZH |
| Package QTY | 60 | 60 | 60 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | @2012 TI | TMS320C6654CZH | 850MHZ |
| Width (mm) | 21 | 21 | 21 |
| Length (mm) | 21 | 21 | 21 |
| Thickness (mm) | 2.42 | 2.42 | 2.42 |
| Mechanical Data | Download | Download | Download |
Parametrics
| Applications | Grid Infrastructure,Machine Vision |
| DRAM | DDR3 |
| DSP | 1 C66x |
| DSP MHz | 750,850 Max. |
| EMAC | 10/100/1000 |
| GFLOPS | 12,13.6 |
| On-Chip L2 Cache | 1024 KB |
| Operating Temperature Range | -40 to 100,0 to 85 C |
| Other On-Chip Memory | 1024 KB |
| PCI/PCIe | 2 PCIe Gen2 |
| Package Size: mm2:W x L | See datasheet (FCBGA) PKG |
| Rating | Catalog |
| Serial I/O | I2C,SPI,UART,UPP |
| Total On-Chip Memory | 1088 KB |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TMDSEVM6657
TMS320C6657 Lite Evaluation Modules
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- TI Keystone DSP PCIe SerDes IBIS-AMI ModelsPDF, 4.8 Mb, File published: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface. - SerDes Implementation Guidelines for KeyStone I DevicesPDF, 590 Kb, File published: Oct 31, 2012
The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge - TMS320C66x DSP Generation of Devices (Rev. A)PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
- KeyStone I DDR3 Initialization (Rev. E)PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP - Hardware Design Guide for KeyStone Devices (Rev. C)PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
- AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)PDF, 2.2 Mb, Revision: A, File published: May 1, 2004
Application Note 1281 Bumped Die (Flip Chip) Packages - SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, File published: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, File published: Dec 13, 2011
- Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, File published: Nov 9, 2010
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Optimizing Loops on the C66x DSPPDF, 585 Kb, File published: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
- TI DSP BenchmarkingPDF, 62 Kb, File published: Jan 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms. - Plastic Ball Grid Array [PBGA] Application Note (Rev. B)PDF, 1.6 Mb, Revision: B, File published: Aug 13, 2015
Model Line
Series: TMS320C6654 (4)
- TMS320C6654CZH7 TMS320C6654CZH8 TMS320C6654CZHA7 TMS320C6654CZHA8
Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP
