Datasheet Texas Instruments SN74LVT125NSR

3.3-V ABT Quadruple Bus Buffers With 3-State Outputs 14-SO -40 to 85

Datasheets

PDF, 673 Kb, Revision: F, File published: Oct 13, 2003

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Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

Bits	4
F @ Nom Voltage(Max)	100 Mhz
ICC @ Nom Voltage(Max)	0.007 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	-32/64 mA
Package Group	SOIC,SSOP,TSSOP
Package Size: mm2:W x L	14SOIC: 52 mm2: 6 x 8.65(SOIC),14SSOP: 48 mm2: 7.8 x 6.2(SSOP),14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	4 ns

RoHS

Compliant

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PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
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PDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Series: SN74LVT125 (13)

Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver