Datasheet Texas Instruments TMS320C6457CCMHA2

Manufacturer	Texas Instruments
Series	TMS320C6457
Part Number	TMS320C6457CCMHA2

Communications Infrastructure Digital Signal Processor 688-FCBGA -40 to 95

Datasheets

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PDF, 2.6 Mb, Revision: B, File published: Jul 9, 2010

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TMS320C6457
Communications Infrastructure Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters. Literature Number: SPRS582B
July 2010 TMS320C6457
Data Manual
SPRS582BвЂ”July 2010 www.ti.com Release History
Additions/Modifications/Deletions 2 SPRS582B Added 850 mHz clock speed. Added content to the Warm Reset section describing how to preserve contents of DDR2 SDRAM through a Warm Reset
cycle with Self-Refresh mode enabled on the SDRAM. Corrected typo in the Reset Timing Requirements table, parameter number 2: changed RESETx to RESET and POR to POR. Corrected 1.2-V to 1.1-V in last item of Features bullet list. SPRS582A Corrected CORECLK(P|N) and ALTCORECLK max frequency, minimum period time, duty cycle, and transition times Corrected Period Jitter tolerance, duty cycle, and transition times for DDRREFCLK(P|N) and ALTDDRCLK Corrected PLL2 block diagram to include correct reference to PLLV2 voltage net Added DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) min and max frequency to PLL2 Clock Frequency Ranges table Removed PLLOUT term from the PLL2 Clock Frequency ranges table Clarified wording in the introduction of the PLL2 section and on the effective x5 multiplier that generates
DDR2CLKOUT0(N|P) and DDR2CLKOUT0(N|P) from DDRREFCLK(P|N) or ALTDDRCLK Added Table 7-4 Power Supply to Peripheral I/O Mapping to clarify the exact I/O and reference clock buffers each power
supply provides power for Added Overshoot/Undershoot definition to Table 6-1 Absolute Maximum Ratings Fixed typo in Table 2-1 under the 1.2 GHz space, вЂњ1.2 V, 1.8 V, and 3.3 VвЂќ now correctly reads вЂњ1.1 V, 1.8 V, and 3.3 VвЂќ Fixed typo for the McBSP timing parameters. вЂњP = 1/CORECLKвЂќ now correctly reads вЂњP = 1/SYSREFCLKвЂќ Fixed typo in 7.3.1 Power-Supply Sequencing -The SPRAAG5 reference now correctly references SPRAAV7 SPRS582 Initial version Release History 2009 Texas Instruments Incorporated TMS320C6457
Communications Infrastructure Digital Signal Processor
SPRS582BвЂ”July 2010 www.ti.com Contents
1 TMS320C6457 Features .11
1.1 TMS320C6457CMH/GMH BGA Package (Bottom View) .12
1.2 Description .12
1.3 Functional Block Diagram .14 2 Device Overview .15
2.1
2.2
2.3
2.4
2.5 …

Prices

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	688	688	688
Package Type	CMH	CMH	CMH
Package QTY	60	60	60
Carrier	JEDEC TRAY (5+1)	JEDEC TRAY (5+1)	JEDEC TRAY (5+1)
Device Marking	TMS320C6457CMH	A1.2GHZ	@2007 TI
Width (mm)	23	23	23
Length (mm)	23	23	23
Thickness (mm)	2.35	2.35	2.35
Mechanical Data	Download	Download	Download

Eco Plan

RoHS

Compliant

Design Kits & Evaluation Modules

Development Kits: TMDSEVM6472
TMS320C6472 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
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JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs)
JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)

Application Notes

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TMS320C6457/TMS320TCI6484/TMS320TCI6487/88 DDR2 Implementation Guidelines (Rev. D)
PDF, 139 Kb, Revision: D, File published: Jan 28, 2010
This document provides implementation instructions for the DDR2 interface contained on the C6457/TCI6484/TCI6487/88 DSP.
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TMS320TCI6484 and TMS320C6457 SERDES Implementation Guidelines (Rev. A)
PDF, 245 Kb, Revision: A, File published: Oct 8, 2009
This document contains implementation instructions for the two serializer/deserializer-based interfaces (SerDes) on the TMS320TCI6484 and TMS320C6457 DSP devices:Serial RapidIOВ® (SRIO)Serial Gigabit Media Independent Interface (SGMII)
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TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (Rev. B)
PDF, 648 Kb, Revision: B, File published: Oct 8, 2009
This application note describes hardware system design considerations for the TMS320TCI6484 and TMS320C6457 DSPs.
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TMS320C6457 Power Consumption Application Report (Rev. A)
PDF, 180 Kb, Revision: A, File published: Mar 25, 2011
This document discusses the power consumption of the Texas Instruments TMS320C6457 digital signal processor (DSP). The power consumption of the device is highly application-dependent. Therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as power supply desig
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Tuning VCP2 and TCP2 Bit Error Rate Performance
PDF, 293 Kb, File published: Feb 11, 2011
In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
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Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
PDF, 80 Kb, Revision: A, File published: Jul 19, 2013
This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
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TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
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Introduction to TMS320C6000 DSP Optimization
PDF, 535 Kb, File published: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

Model Line

Series: TMS320C6457 (7)

TMS320C6457CCMH TMS320C6457CCMH2 TMS320C6457CCMH8 TMS320C6457CCMHA TMS320C6457CCMHA2 TMS320C6457CGMHA TMS320C6457CGMHA2

Manufacturer's Classification

Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP