Datasheet Texas Instruments SN74HC193NE4
| Manufacturer | Texas Instruments |
| Series | SN74HC193 |
| Part Number | SN74HC193NE4 |
4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-PDIP -40 to 85
Datasheets
SN54HC193, SN74HC193 datasheet
PDF, 1.1 Mb, Revision: D, File published: Oct 2, 2003
Extract from the document
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | SN74HC193N |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Download |
Parametrics
| Bits | 4 |
| F @ Nom Voltage(Max) | 28 Mhz |
| Function | Counter |
| ICC @ Nom Voltage(Max) | 0.08 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 5.2/-5.2 mA |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Technology Family | HC |
| Type | Binary |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 55 ns |
Eco Plan
| RoHS | Compliant |
| Pb Free | Yes |
Application Notes
- HCMOS Design Considerations (Rev. A)PDF, 207 Kb, Revision: A, File published: Sep 9, 2002
This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.
Model Line
Series: SN74HC193 (12)
Manufacturer's Classification
- Semiconductors > Logic > Specialty Logic > Counter/Arithmetic/Parity Function
