Datasheet Texas Instruments 5962-0720601VXC
| Manufacturer | Texas Instruments |
| Series | ADS5424-SP |
| Part Number | 5962-0720601VXC |
14-Bit, 125-MSPS Analog-to-Digital Converter (ADC)- Class V 52-CFP -55 to 125
Datasheets
Class V, 14 Bit, 105 MSPS Analog-to-Digital Converter datasheet
PDF, 436 Kb, Revision: D, File published: Sep 16, 2013
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 52 |
| Package Type | HFG |
| Industry STD Term | CFP |
| JEDEC Code | S-PQFP-F |
| Package QTY | 1 |
| Width (mm) | 13.97 |
| Length (mm) | 13.97 |
| Thickness (mm) | 3.42 |
| Pitch (mm) | 0.64 |
| Max Height (mm) | 3.42 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 1 |
| Analog Voltage AVDD(Max) | 5.25 V |
| Analog Voltage AVDD(Min) | 4.75 V |
| Architecture | Pipeline |
| Digital Supply(Max) | 3.6 V |
| Digital Supply(Min) | 3 V |
| ENOB | 11.5 Bits |
| INL(Max) | 6.9 +/-LSB |
| INL(Typ) | 3 +/-LSB |
| Interface | Parallel CMOS |
| Operating Temperature Range | -55 to 125,25 Only C |
| Package Group | CFP |
| Package Size: mm2:W x L | See datasheet (CFP) PKG |
| Power Consumption(Typ) | 1900 mW |
| Rating | Space |
| Reference Mode | Int |
| Resolution | 14 Bits |
| SFDR | 81.6 dB |
| SNR | 72.4 dB |
Eco Plan
| RoHS | See ti.com |
Application Notes
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
Model Line
Series: ADS5424-SP (2)
- 5962-0720601VXC ADS5424HFG/EM
Manufacturer's Classification
- Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters
Other Names:
59620720601VXC, 5962 0720601VXC
