Multicore Digital Signal Processor 561-FC/CSP -40 to 95
PDF, 288 Kb, File published: Oct 14, 2008
The TMS320C6474 DSP integrates three 1-GHz C64x+ DSP CPU cores, a host of high-speed peripherals, and large amounts of internal memory in a compact 23 mm by 23 mm package. These features allow the C6474 device to provide significant performance integration and high-performance density, along with substantial efficiencies in power, cost, and board space.
PDF, 85 Kb, File published: Oct 14, 2008
This document discusses the power consumption of the Texas Instruments TMS320C6474 digital signal processor (DSP). The power consumption on the TMS320C6474 device is highly application-dependent; therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as power
PDF, 140 Kb, File published: Oct 14, 2008
This document provides information on the C6474 module throughput.
PDF, 30 Kb, File published: Aug 28, 2009
This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:http://www.tiexpressdsp.com/index.php/DIO_LibraryThis DIO library aims at providing a CSL-like Serial RapidIO (SRIO) functional layer for the directIO mode of Texas Instruments' TMS320C64
PDF, 127 Kb, File published: Oct 14, 2008
This document contains implementation instructions for the three serializer/deserializer (SERDES) based interfaces on the TMS320C6474 DSP device. These include the Serial RapidIOВ® (SRIO), antenna, and serial gigabit media independent interface (SGMII) interfaces.Serial RapidIO is an industry-standard high-speed switched-packet interconnect. The antenna interface is compatible with two industr
PDF, 381 Kb, Revision: B, File published: Aug 3, 2010
This document describes hardware system design considerations for the TMS320C6474 device.
PDF, 28 Kb, File published: Aug 28, 2009
This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:http://tiexpressdsp.com/index.php/AIFThis article was designed for both beginners and advanced users of the Antenna Interface in the embedded processor TMS320C6474 chip support software library. It i
PDF, 96 Kb, Revision: A, File published: Aug 4, 2009
This document provides implementation instructions for the DDR2 interface contained on the C6474 DSP device.
PDF, 961 Kb, File published: Jan 12, 2009
Inter-core (also called Inter-CPU or Inter-Processor) communication on the C6474 multi-core DSP devices can be accomplished using the on-chip inter-processor communication (IPC) module. The main function of the IPC module is to provide inter-core interrupts. Optionally, flags can be sent along with an interrupt for implementation or more advanced inter-core communication protocols.The purpose o
PDF, 27 Kb, File published: Aug 28, 2009
This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute, visit this topic at:href=http://wiki.davincidsp.com/index.php/AIF_Inter_DSP_CommunicationThe TMS320C6474 Antenna Interface (AIF) is a CPRI and OBSAI-compliant peripheral whose primary purpose
PDF, 73 Kb, File published: Oct 14, 2008
This application report presents common bus architecture protocols and components as main factors for generic throughput analysis. It provides necessary details on the internal bus structure which enables you to estimate system-on-chip (SoC) performance for a given application.
PDF, 142 Kb, File published: Jan 27, 2009
Today's digital signal processor (DSP) architectures are confronted with the tough requirement of addressing a wide-range of standards and meeting a cost-effective performance/power trade-off. Increasing raw million instructions per second (MIPS) performance just by running at a higher frequency is not possible anymore since leakage is becoming a dominant factor with shrinking silicon geometries.
PDF, 614 Kb, File published: Dec 17, 2008
The TPS40197 reference design is a synchronous buck converter providing VID programmable output voltage from 0.9 V to 1.2 V at up to 7 A from a 12-V or 5-V bus (4.75 V ~ 13.2 V). The design uses the TPS40197 – a synchronous buck controller with 4-bit VID interface for Smart-Reflex™ DSPs.
PDF, 107 Kb, File published: Sep 30, 2008
PDF, 131 Kb, File published: Oct 1, 2008
PDF, 311 Kb, File published: Oct 14, 2008
The TMS320C6455 fixed-point digital signal processor (DSP) and the TMS320C6474 communications infrastructure DSP are two of Texas Instruments’ high-performance DSP processors, each offering high-speed DSP processing, large internal memories, a rich set of peripherals, and other support functions useful in a system environment.This application report describes device considerations for migrati
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293 Kb, File published:
Feb 11, 2011In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
PDF, 80 Kb, Revision: A, File published: Jul 19, 2013
This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
PDF, 292 Kb, Revision: A, File published: Aug 21, 2008
This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+в„ў DSP devices and the EDMA2 used on TMS320C64xв„ў DSP devices, and provides guidance for migrating from EDMA2 to EDMA3.
PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
PDF, 535 Kb, File published: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then
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Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP
