Datasheet Texas Instruments CD74HC4046APWR
| Manufacturer | Texas Instruments |
| Series | CD74HC4046A |
| Part Number | CD74HC4046APWR |
High Speed CMOS Logic Phase-Locked-Loop with VCO 16-TSSOP -55 to 125
Datasheets
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet
PDF, 833 Kb, Revision: J, File published: Nov 21, 2003
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | HJ4046A |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Bits | 1 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 0.08 mA |
| Operating Temperature Range | -55 to 125 C |
| Output Drive (IOL/IOH)(Max) | 5.2/-5.2 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 64 ns |
Eco Plan
| RoHS | Compliant |
Application Notes
- Implementation of FSK Modulation and Demodulation using CD74HC4046APDF, 1.3 Mb, File published: Nov 25, 2013
- CMOS Phase-Locked-Loop Applications (Rev. B)PDF, 687 Kb, Revision: B, File published: Sep 19, 2002
Applications of the HC/HCT4046A phase-locked loop (PLL) and HC/HCT7046A PLL with lock detection are provided including design examples with calculated and measured results. Features of these devices relative to phase comparators lock indicators voltage-controlled oscillators (VCOs) and filter design are presented. - Generating Low Phase-Noise Clocks for Audio Data Converters from Low FrequencyPDF, 860 Kb, File published: Mar 31, 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica - Selecting the Right Texas Instruments Signal SwitchPDF, 769 Kb, File published: Sep 7, 2001
Texas Instruments offers a wide variety of electronic switches (digital analog bilateral bilateral analog) in a variety of families including CBT CBTLV HC LV and LVC. Depending on the application the right solution may be an analog switch that passes digital signals or vice versa. This application report summarizes the various switching technologies and provides considerations for choosi - SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
Model Line
Series: CD74HC4046A (15)
Manufacturer's Classification
- Semiconductors > Logic > Specialty Logic > Phase-Locked-Loop (PLL)/Oscillator
