Datasheet Texas Instruments SMJ320C31HFGM50

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  How TMS320 Tools Interact With the TMS320C32's Enhanced Memory Interface
  PDF, 160 Kb, File published: Nov 1, 1995
  This document describes using the TMS320 floating-point digital signal processor (DSP) optimizing C compiler and assembly language tools with the variable memory width and data sizes supported by the TMS320C32 ('C32) 32-bit DSP. An overview of the 'C32 strobe control registers is presented along with their configuration for use with a compiler linker or debugger. Different memory configurations
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  FIFO Synchronous Retransmit: Programmable DSP-Interface for FIR Filtering (Rev. A)
  PDF, 76 Kb, Revision: A, File published: Mar 1, 1996
  The SN74ACT3638 FIFO contains a patented synchronous retransmit feature which allows data stored within the FIFO to be re-read starting at a selected position. This document shows the use of the retransmit feature with a digital signal processor (DSP) for finite impulse response (FIR) filtering. The application uses the 32-bit floating-point TMS320C31 and a SN74ACT3638 bi-directional clocked FIFO
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  Interfacing Memory to the TMS320C32 DSP (Rev. A)
  PDF, 376 Kb, Revision: A, File published: May 1, 1996
  The low-cost of the TMS320C32 (?C32) makes 32-bit floating-point digital signal processing (DSP) available to a wider variety of applications than ever before. This document explains in detail the features of the ?C32 enhanced memory interface with design examples for 32- 16- and 8-bit-wide external memories. Comprehensive diagrams show precise operation of the processor and complete circuits fo
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  Interfacing TI Clocked FIFOs With TI Floating-Point DSPs (Rev. A)
  PDF, 108 Kb, Revision: A, File published: Mar 1, 1996
  FIFO memories are used in digital signal processing systems for matching data paths with asynchronous clock or data rates. This document shows the SN74ACT3632 512?36?2 clocked FIFO as a single-chip bi-directional buffering solution that interfaces to the TI TMS320C3x and TMS320C4x floating-point DSP family. Programmable FIFO flags enable DMA control techniques that are used to handle the data flow
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  Engine Knock Detection Using Spectral Analysis With TMS320C25 or TMS320C30 DSPs
  PDF, 254 Kb, File published: Jan 1, 1995
  An efficient method of detecting combustion engine knock is using spectral analysis. The detection process algorithm adapts to a no-knock reference at varying speeds and loads by using multiple frequencies. This document presents an problem overview current technology and two implementation examples are given to aid in the development of system specific hardware and software. The first system is
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  320C3x 320C4x and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D)
  PDF, 248 Kb, Revision: D, File published: Aug 6, 2004
  System board-level design and end-equipment environments can impact the operation of specific commercial and military 320C3x (320C30 320C31 320LC31 320C32 and 320VC33) 320C4x (320C40 and 320C44) digital signal processors (DSPs) and the military 320MCM42x (320MCM42C and 320MCM42D) multichip modules (MCMs) during power up. The 320MCM42x MCM incorporates two 320C40 DSP die.Specifically the s
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  Setting Up TMS320 DSP Interrupts in 'C'
  PDF, 168 Kb, File published: Nov 1, 1994
  Four steps are required to set the TMS320 DSP interrupts: create a interrupt service routine initialize the vector table and set the memory map enable the interrupts in the CPU and enable the interrupt sources. This document shows how to set the interrupts in C C callable assembly or in-line C. Sample C code segments are provided. The appendix gives complete examples for setting interrupt vec

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Manufacturer's Classification

• Semiconductors > Processors > Digital Signal Processors > Other High Reliability DSPs