Datasheet Texas Instruments TLV2548MFKB
| Manufacturer | Texas Instruments |
| Series | TLV2548M |
| Part Number | TLV2548MFKB |
12-Bit 200 kSPS ADC Ser. Out, Auto Pwrdn (S/W and H/W), Low Power W/8 x FIFO W/8 Ch. 20-LCCC -55 to 125
Datasheets
3-V to 5.5-V, 12-Bit, 200-KSPS, 4-/8-Channel, Low-Power Serial Analog-to-Digital datasheet
PDF, 1.6 Mb, Revision: F, File published: Oct 7, 2009
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 20 | 20 | 20 | 20 |
| Package Type | FK | FK | FK | FK |
| Industry STD Term | LCCC | LCCC | LCCC | LCCC |
| JEDEC Code | S-CQCC-N | S-CQCC-N | S-CQCC-N | S-CQCC-N |
| Package QTY | 1 | 1 | 1 | 1 |
| Carrier | TUBE | TUBE | TUBE | TUBE |
| Device Marking | TLV2548 | 5962- | MFKB | 9957001Q2A |
| Width (mm) | 8.89 | 8.89 | 8.89 | 8.89 |
| Length (mm) | 8.89 | 8.89 | 8.89 | 8.89 |
| Thickness (mm) | 1.83 | 1.83 | 1.83 | 1.83 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 2.03 | 2.03 | 2.03 | 2.03 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| # Input Channels | 8 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 3 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 3 V |
| ENOB | 11.6 Bits |
| INL(Max) | 1.2 +/-LSB |
| Interface | SPI |
| Operating Temperature Range | -55 to 125 C |
| Package Group | LCCC |
| Package Size: mm2:W x L | 20LCCC: 79 mm2: 8.89 x 8.89(LCCC) PKG |
| Power Consumption(Typ) | 3.3 mW |
| Rating | Military |
| Reference Mode | Ext,Int |
| Resolution | 12 Bits |
| SFDR | 84 dB |
| SNR | 70 dB |
| Sample Rate (max) | 200kSPS SPS |
Eco Plan
| RoHS | See ti.com |
Application Notes
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
Model Line
Series: TLV2548M (2)
- 5962-9957001Q2A TLV2548MFKB
Manufacturer's Classification
- Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters
