Datasheet Texas Instruments ADS7223SRHBT
| Manufacturer | Texas Instruments |
| Series | ADS7223 |
| Part Number | ADS7223SRHBT |
12-bit 1MSPS 4x2/2x2 Simultaneous Sampling SAR ADC 32-VQFN -40 to 125
Datasheets
ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4Г—2 or 2Г—2 Channel, Simultaneous Sampling Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, Revision: D, File published: Sep 2, 2017
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 32 | 32 |
| Package Type | RHB | RHB |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 250 | 250 |
| Carrier | SMALL T&R | SMALL T&R |
| Device Marking | 7223 | ADS |
| Width (mm) | 5 | 5 |
| Length (mm) | 5 | 5 |
| Thickness (mm) | .9 | .9 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | Download | Download |
Parametrics
| # Input Channels | 4 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 2.3 V |
| INL(Max) | 0.5 +/-LSB |
| Input Range(Max) | 5.5 V |
| Input Type | Differential,Pseudo-Differential |
| Integrated Features | N/A |
| Interface | SPI |
| Multi-Channel Configuration | Multiplexed,Simultaneous Sampling |
| Operating Temperature Range | -40 to 125 C |
| Package Group | VQFN |
| Package Size: mm2:W x L | 32VQFN: 25 mm2: 5 x 5(VQFN) PKG |
| Power Consumption(Typ) | 47.2 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 12 Bits |
| SINAD | 72 dB |
| SNR | 73 dB |
| Sample Rate (max) | 1MSPS SPS |
| Sample Rate(Max) | 1 MSPS |
| THD(Typ) | -86 dB |
Eco Plan
| RoHS | Compliant |
Application Notes
- Using the Sequencer and Pseudo-Differential Features of the ADS8363PDF, 161 Kb, File published: May 21, 2014
- Interfacing to the ADS8363 Pseudo-Differential Operating ModePDF, 548 Kb, File published: Aug 4, 2014
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
Model Line
Series: ADS7223 (2)
- ADS7223SRHBR ADS7223SRHBT
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)
