Datasheet Texas Instruments SN74LVTH16240DGGR

ManufacturerTexas Instruments
SeriesSN74LVTH16240
Part NumberSN74LVTH16240DGGR
Datasheet Texas Instruments SN74LVTH16240DGGR

3.3-V ABT 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85

Datasheets

SN54LVTH16240, SN74LVTH16240 datasheet
PDF, 347 Kb, Revision: D, File published: Dec 1, 2006
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin48
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVTH16240
Width (mm)6.1
Length (mm)12.5
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDownload

Parametrics

Bits16
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)0.005 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)-32/64 mA
Package GroupTSSOP
Package Size: mm2:W x L48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)4 ns

Eco Plan

RoHSCompliant

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, File published: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Manufacturer's Classification

  • Semiconductors > Logic > Buffer/Driver/Transceiver > Inverting Buffer/Driver