Datasheet Texas Instruments CD74HC109M96

Manufacturer	Texas Instruments
Series	CD74HC109
Part Number	CD74HC109M96

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125

Datasheets

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PDF, 458 Kb, Revision: E, File published: Oct 13, 2003

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	16
Package Type	D
Industry STD Term	SOIC
JEDEC Code	R-PDSO-G
Package QTY	2500
Carrier	LARGE T&R
Device Marking	HC109M
Width (mm)	3.91
Length (mm)	9.9
Thickness (mm)	1.58
Pitch (mm)	1.27
Max Height (mm)	1.75
Mechanical Data	Download

Parametrics

Bits	2
F @ Nom Voltage(Max)	70 Mhz
ICC @ Nom Voltage(Max)	0.04 mA
Output Drive (IOL/IOH)(Max)	-6/6 mA
Package Group	SOIC
Package Size: mm2:W x L	16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	HC
VCC(Max)	6 V
VCC(Min)	2 V
Voltage(Nom)	3.3,5 V
tpd @ Nom Voltage(Max)	53 ns

Eco Plan

RoHS

Compliant

Application Notes

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PDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal

Model Line

Series: CD74HC109 (7)

CD74HC109E CD74HC109EE4 CD74HC109M CD74HC109M96 CD74HC109M96E4 CD74HC109ME4 CD74HC109MG4

Manufacturer's Classification

Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop