Datasheet Texas Instruments TMS320VC5506GHH

ManufacturerTexas Instruments
SeriesTMS320VC5506
Part NumberTMS320VC5506GHH
Datasheet Texas Instruments TMS320VC5506GHH

Fixed-Point Digital Signal Processor 179-BGA MICROSTAR -40 to 85

Datasheets

TMS320VC5506 Fixed-Point Digital Signal Processor datasheet
PDF, 1.7 Mb, Revision: C, File published: Jan 23, 2008
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin179179
Package TypeGHHGHH
Industry STD TermBGA MICROSTARBGA MICROSTAR
JEDEC CodeS-PBGA-NS-PBGA-N
Package QTY160160
CarrierEIAJ TRAY (5+1)EIAJ TRAY (5+1)
Device MarkingVC5506GHHTMS320
Width (mm)1212
Length (mm)1212
Thickness (mm).9.9
Pitch (mm).8.8
Max Height (mm)1.41.4
Mechanical DataDownloadDownload

Parametrics

ApplicationsAudio,Automotive,Communications and Telecom,Consumer Electronics,Industrial
DRAMSDRAM
DSP1 C55x
DSP MHz108 Max.
I2C1
McBSP3
Operating SystemsDSP/BIOS,VLX
Operating Temperature Range-40 to 85 C
RatingCatalog
USB1

Eco Plan

RoHSSee ti.com

Design Kits & Evaluation Modules

  • JTAG Emulators/ Analyzers: TMDSEMU200-U
    XDS200 USB Debug Probe
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU100V2U-20T
    XDS100v2 JTAG Debug Probe (20-pin cTI version)
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU100V2U-14T
    XDS100v2 JTAG Debug Probe (14-pin TI version)
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
    XDS560v2 System Trace USB & Ethernet Debug Probe
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
    XDS560v2 System Trace USB Debug Probe
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Programming the TMS320VC5503/C5506/C5507/C5509/C5509A I2C Peripheral (Rev. A)
    PDF, 157 Kb, Revision: A, File published: Sep 26, 2008
    This application report demonstrates the procedure used to program the TMS320VC5503/C5506/C5507/C5509/C5509A inter-integrated circuit (I2C) peripheral module. Basic operations of the I2C, including reading and writing, and the initialization of the I2C bus are covered. These operations are illustrated using the I2C routines provided in the chip support library (CSL). For more information, see the
  • TMS320VC5509A DSP Hardware Designer's Resource Guide
    PDF, 197 Kb, File published: Jun 29, 2004
    The DSP Hardware Designer?s Resource Guide is organized by development flow and functional areas to make your design effort as seamless as possible. Topics covered include getting started, board design, system testing, and checklists to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, models, symbols, and refere
  • Using the TMS320VC5506/C5507/C5509/C5509A USB Bootloader (Rev. C)
    PDF, 304 Kb, Revision: C, File published: Oct 1, 2008
    Bootloading the TMS320VC5506/C5507/C5509/C5509A digital signal processor (DSP) through the on-chip universal serial bus (USB) peripheral is part of the standard bootloader provided on the device. This document describes the procedures for physically connecting the DSP to a USB host, invoking the USB bootloader on the DSP, generating the correct boot table file, and downloading the boot table from
  • Disabling the Internal Oscillator on the TMSVC5503/C5506/C5507/C5509/C5509A DSP (Rev. D)
    PDF, 99 Kb, Revision: D, File published: Sep 9, 2008
    This application report contains information and examples on how to disable the internal clock oscillator on the TMS320VC5503, TMS320VC5506, TMS320VC5507, TMS320VC5509, and TMS320VC5509A DSPs to minimize power consumption. The document contains an overview of how the internal clock oscillator operates, and how to disable it as part of the IDLE power-down feature. It also discusses how to wake up t
  • Using the USB APLL on the TMS320VC5506/C5507/C5509A (Rev. B)
    PDF, 102 Kb, Revision: B, File published: Sep 9, 2008
    This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DP
  • Using the TMS320VC5503/C5506/C5507/C5509/C5509A Bootloader (Rev. F)
    PDF, 222 Kb, Revision: F, File published: Sep 5, 2008
    This document describes the features of the on-chip bootloder provided with the TMS320VC5503/C5506/C5507/C5509/C5509A digital signal processor (DSP). Included are descriptions of each of the available boot modes and any interfacing requirements associated with them as well as instructions on generating the boot table.
  • Recommended Power Solutions For TMS320C5509A/07/03
    PDF, 37 Kb, File published: Mar 28, 2005
  • TMS320VC5503/VC5506/VC5507/C5509A Power Consumption Summary (Rev. C)
    PDF, 107 Kb, Revision: C, File published: Sep 5, 2008
    This document assists in the estimation of power consumption for the TMS320VC5503/C5506/C5507/C5509A digital signal processors (DSPs). Power consumption on these devices is highly application-dependent, so a spreadsheet is provided to model power consumption. The spreadsheet allows you to enter parameters that closely resemble the application and generate a realistic estimate of DSP power consumpt
  • Board and System Design Considerations for the TMS320VC5503/06/07/09A DSPs
    PDF, 120 Kb, File published: Nov 19, 2008
    An effective system-level board design requires termination of specific pins and taking advantage of idle and power-down modes on these low power VC5503/5506/5507/5509A digital signal processors (DSPs). This can be achieved by controlling unused pins and dynamically turning off all peripherals and internal functional units when not in use. The benefit is that the DSP and application consume only a
  • Common Object File Format (COFF)
    PDF, 125 Kb, File published: Apr 15, 2009
  • High-Speed Interface Layout Guidelines (Rev. G)
    PDF, 814 Kb, Revision: G, File published: Jul 27, 2017
    As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

Model Line

Manufacturer's Classification

  • Semiconductors > Processors > Digital Signal Processors > C5000 DSP > C55x DSP