Datasheet Texas Instruments ADS5272IPFP

Manufacturer	Texas Instruments
Series	ADS5272
Part Number	ADS5272IPFP

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Design Kits & Evaluation Modules

• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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Application Notes

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  Ultrasound Receive Chain Evaluation Module
  PDF, 49 Kb, File published: Jul 14, 2006
  A prototype system for the receive signal chain of an ultrasound system is described. This prototype system is available to customers as an evaluation module that can be ordered from TI's Web site.
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  LVDS Outputs on the ADS527x
  PDF, 236 Kb, File published: Jun 10, 2004
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  Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
  PDF, 67 Kb, File published: Feb 23, 2005
  The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
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  Interfacing the VCA8613 with High-Speed ADCs
  PDF, 78 Kb, File published: Apr 5, 2005
  The VCA8613 is an 8-channel variable gain amplifier ideally suited for portable and mid-range ultrasound applications. Each channel consists of a Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The VGA contains two parts: a voltage-controlled attenuator (VCA) and a programmable gain amplifier (PGA). The PGA output feeds directly into an integrated 2-pole low-pass Butterworth filter.
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  Interfacing the VCA8617 with High-Speed ADCs
  PDF, 72 Kb, File published: Apr 5, 2005
  The VCA8617 is an 8-channel variable gain amplifier ideally suited for portable and mid-range ultrasound applications. Each channel consists of a Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The VGA contains two parts: a voltage-controlled attenuator and a programmable gain amplifier. The PGA output feeds directly into an integrated 3-pole low-pass Butterworth filter, which preve
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  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, File published: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
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  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
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  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Manufacturer's Classification

• Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)