Datasheet Texas Instruments ADS901E

Manufacturer	Texas Instruments
Series	ADS901
Part Number	ADS901E

10-Bit, 20-MSPS Analog-to-Digital Converter (ADC) 28-SSOP -40 to 85

Datasheets

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PDF, 254 Kb, Revision: A, File published: Feb 23, 2001

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	28
Package Type	DB
Industry STD Term	SSOP
JEDEC Code	R-PDSO-G
Package QTY	50
Carrier	TUBE
Device Marking	ADS901E
Width (mm)	5.3
Length (mm)	10.2
Thickness (mm)	1.95
Pitch (mm)	.65
Max Height (mm)	2
Mechanical Data	Download

Parametrics

# Input Channels	1
Analog Input BW	100 MHz
Architecture	Pipeline
DNL(Max)	1 +/-LSB
DNL(Typ)	0.8 +/-LSB
ENOB	8 Bits
INL(Max)	3.5 +/-LSB
INL(Typ)	3.5 +/-LSB
Input Buffer	No
Input Range	1,2 Vp-p
Interface	Parallel CMOS
Operating Temperature Range	-40 to 85 C
Package Group	SSOP
Package Size: mm2:W x L	28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG
Power Consumption(Typ)	49 mW
Rating	Catalog
Reference Mode	Ext
Resolution	10 Bits
SFDR	49 dB
SINAD	50 dB
SNR	53 dB
Sample Rate(Max)	20 MSPS

Eco Plan

RoHS

Compliant

Design Kits & Evaluation Modules

Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
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Application Notes

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CDCE62005 as Clock Solution for High-Speed ADCs
PDF, 805 Kb, File published: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
PDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
PDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Model Line

Series: ADS901 (1)

ADS901E

Manufacturer's Classification

Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)