Datasheet Texas Instruments 74ACT11030

ManufacturerTexas Instruments
Series74ACT11030
Datasheet Texas Instruments 74ACT11030

8-Input Positive-NAND Gates

Datasheets

8-Input Positive-NAND Gates datasheet
PDF, 387 Kb, File published: Apr 1, 1993
Extract from the document

Prices

Status

74ACT11030D74ACT11030DE474ACT11030DR74ACT11030DRG474ACT11030N
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

Packaging

74ACT11030D74ACT11030DE474ACT11030DR74ACT11030DRG474ACT11030N
N12345
Pin1414141414
Package TypeDDDDN
Industry STD TermSOICSOICSOICSOICPDIP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDIP-T
Package QTY50502500250025
CarrierTUBETUBELARGE T&RLARGE T&RTUBE
Device MarkingACT11030ACT11030ACT11030ACT1103074ACT11030N
Width (mm)3.913.913.913.916.35
Length (mm)8.658.658.658.6519.3
Thickness (mm)1.581.581.581.583.9
Pitch (mm)1.271.271.271.272.54
Max Height (mm)1.751.751.751.755.08
Mechanical DataDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / Models74ACT11030D
74ACT11030D
74ACT11030DE4
74ACT11030DE4
74ACT11030DR
74ACT11030DR
74ACT11030DRG4
74ACT11030DRG4
74ACT11030N
74ACT11030N
Bits11111
F @ Nom Voltage(Max), Mhz9090909090
ICC @ Nom Voltage(Max), mA0.040.040.040.040.04
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-24
Package GroupSOICSOICSOICSOICPDIP
Package Size: mm2:W x L, PKG14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)See datasheet (PDIP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyACTACTACTACTACT
VCC(Max), V5.55.55.55.55.5
VCC(Min), V4.54.54.54.54.5
Voltage(Nom), V55555
tpd @ Nom Voltage(Max), ns8.78.78.78.78.7

Eco Plan

74ACT11030D74ACT11030DE474ACT11030DR74ACT11030DRG474ACT11030N
RoHSCompliantCompliantCompliantCompliantCompliant
Pb FreeYes

Application Notes

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Introduction to Logic
    PDF, 93 Kb, File published: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, Revision: D, File published: Jun 23, 2016
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, File published: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, File published: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, File published: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Gate> NAND Gate