Datasheet Texas Instruments ADC12D1000RF
| Manufacturer | Texas Instruments |
| Series | ADC12D1000RF |
12-Bit, Dual 1.0-GSPS or Single 2.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)
Datasheets
ADC12D1x00RF 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC datasheet
PDF, 3.5 Mb, Revision: H, File published: Aug 31, 2015
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Status
| ADC12D1000RFIUT/NOPB | |
|---|---|
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| ADC12D1000RFIUT/NOPB | |
|---|---|
| N | 1 |
| Pin | 292 |
| Package Type | NXA |
| Industry STD Term | BGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 40 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ADC12D1000RFIUT |
| Width (mm) | 27 |
| Length (mm) | 27 |
| Thickness (mm) | 2.38 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.4 |
| Mechanical Data | Download |
Parametrics
| Parameters / Models | ADC12D1000RFIUT/NOPB |
|---|---|
| # Input Channels | 2,1 |
| Analog Input BW, MHz | 2700 |
| Architecture | Folding Interpolating |
| DNL(Max), +/-LSB | 0.4 |
| DNL(Typ), +/-LSB | 0.4 |
| ENOB, Bits | 9.6 |
| INL(Max), +/-LSB | 2.5 |
| INL(Typ), +/-LSB | 2.5 |
| Input Buffer | Yes |
| Input Range, Vp-p | 0.8 |
| Interface | Parallel LVDS |
| Operating Temperature Range, C | -40 to 85 |
| Package Group | BGA |
| Package Size: mm2:W x L, PKG | 292BGA: 729 mm2: 27 x 27(BGA) |
| Power Consumption(Typ), mW | 3510 |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution, Bits | 12 |
| SFDR, dB | 71.4 |
| SINAD, dB | 59.7 |
| SNR, dB | 60.1 |
| Sample Rate(Max), MSPS | 1000,2000 |
Eco Plan
| ADC12D1000RFIUT/NOPB | |
|---|---|
| RoHS | Compliant |
Application Notes
- From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, File published: Dec 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of MitigatPDF, 720 Kb, File published: Dec 9, 2013
The SFDR performance of an ADC is limited by the largest spur in the spectrum from DC to Fs / 2. These spurs can either be reduced or avoided entirely for maximum SFDR performance, based on the application. This reference design explores the reason behind spurs in the 10-bit and 12-bit GSPS ADCfamily. The specific products covered are: ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12 - AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C)PDF, 60 Kb, Revision: C, File published: May 1, 2013
In order to facilitate upgrading applications from a 10-bit Gig ADC to a 12-bit Gig ADC, the ADC10D1x00(ADC10D1500/ADC10D1000) is designed to be pin-compatible with the ADC12D1x00(ADC12D1800/1600/1000). This means that a single board layout may be designed with both resolutionADCs in mind for more cost efficient and time-to-market product development. - AN-2177 Using the LMH6554 as a ADC Driver (Rev. A)PDF, 1.7 Mb, Revision: A, File published: Apr 26, 2013
This application report discusses the use of the Texas Instruments LMH6554 as an ADC driver. - AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, Revision: G, File published: Feb 3, 2017
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, File published: Oct 29, 2014
Model Line
Series: ADC12D1000RF (1)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
