Datasheet Texas Instruments ADS41B49

Manufacturer	Texas Instruments
Series	ADS41B49

Datasheets

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Status

Packaging

Parametrics

Parameters / Models	ADS41B49IRGZR	ADS41B49IRGZT
# Input Channels	1	1
Analog Input BW, MHz	800	800
Architecture	Pipeline	Pipeline
DNL(Typ), +/-LSB	2.5	2.5
ENOB, Bits	11.5	11.5
INL(Max), +/-LSB	5	5
INL(Typ), +/-LSB	2.5	2.5
Input Buffer	Yes	Yes
Input Range, Vp-p	1.5	1.5
Interface	DDR LVDS,Parallel CMOS	DDR LVDS,Parallel CMOS
Operating Temperature Range, C	-40 to 85	-40 to 85
Package Group	VQFN	VQFN
Package Size: mm2:W x L, PKG	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ), mW	350	350
Rating	Catalog	Catalog
Reference Mode	Int	Int
Resolution, Bits	14	14
SFDR, dB	89	89
SINAD, dB	69.5	69.5
SNR, dB	71.7	71.7
Sample Rate(Max), MSPS	250	250

Eco Plan

Application Notes

• Download
  Power Supply Design for the ADS41xx (Rev. A)
  PDF, 401 Kb, Revision: A, File published: Dec 29, 2011
  System designers traditionally power the high-speed data converter in their systems from a low-noise, low-dropout linear regulator (LDO) in order to achieve the performance described in the analog-to-digital converter (ADC) data sheet. However, LDOs inherently are not very power efficient. Switching regulators, on the other hand, offer good power efficiency but typically come with higher output no
• Download
  High-Speed Analog-to-Digital Converter Basics
  PDF, 1.1 Mb, File published: Jan 11, 2012
  The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
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  Band-Pass Filter Design Techniques for High-Speed ADCs
  PDF, 733 Kb, File published: Feb 27, 2012
  Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the
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  QFN Layout Guidelines
  PDF, 1.3 Mb, File published: Jul 28, 2006
  Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
• Download
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, File published: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Download
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
• Download
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Download
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
• Download
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)