Datasheet Texas Instruments ADS5500

Manufacturer	Texas Instruments
Series	ADS5500

Datasheets

Prices

Status

Packaging

Parametrics

Parameters / Models	ADS5500IPAP	ADS5500IPAPR
# Input Channels	1	1
Analog Input BW, MHz	750	750
Architecture	Pipeline	Pipeline
DNL(Max), +/-LSB	0.75	0.75
DNL(Typ), +/-LSB	0.75	0.75
ENOB, Bits	11.3	11.3
INL(Max), +/-LSB	2.5	2.5
INL(Typ), +/-LSB	2.5	2.5
Input Buffer	No	No
Input Range, Vp-p	2.3	2.3
Interface	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C	-40 to 85	-40 to 85
Package Group	HTQFP	HTQFP
Package Size: mm2:W x L, PKG	64HTQFP: 144 mm2: 12 x 12(HTQFP)	64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW	780	780
Rating	Catalog	Catalog
Reference Mode	Int	Int
Resolution, Bits	14	14
SFDR, dB	83	83
SINAD, dB	71.6	71.6
SNR, dB	72.3	72.3
Sample Rate(Max), MSPS	125	125

Eco Plan

Application Notes

• Download
  14-Bit, 125-MSPS ADS5500 Evaluation
  PDF, 738 Kb, File published: Jan 18, 2005
• Download
  Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
  PDF, 627 Kb, File published: Jun 25, 2004
  Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the
• Download
  Clocking High-Speed Data Converters
  PDF, 310 Kb, File published: Jan 18, 2005
• Download
  Low-power, high-intercept interface to the ADS5424, 105-MSPS converter
  PDF, 478 Kb, File published: Oct 10, 2005
• Download
  ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
  PDF, 273 Kb, File published: Apr 22, 2004
  Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
• Download
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
• Download
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
• Download
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Download
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Download
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Download
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revision: A, File published: May 18, 2015
• Download
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revision: A, File published: Apr 16, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)