Datasheet Texas Instruments ADS5553
| Manufacturer | Texas Instruments |
| Series | ADS5553 |
Dual-Channel, 14-Bit, 65-MSPS Analog-to-Digital Converter (ADC)
Datasheets
Dual 14 Bit, 65 MSPS ADC datasheet
PDF, 625 Kb, File published: Feb 21, 2005
Extract from the document
Prices
Status
| ADS5553IPFP | ADS5553IPFPR | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
Packaging
| ADS5553IPFP | ADS5553IPFPR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 80 | 80 |
| Package Type | PFP | PFP |
| Industry STD Term | HTQFP | HTQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 96 | 1000 |
| Carrier | JEDEC TRAY (10+1) | LARGE T&R |
| Device Marking | ADS5553I | ADS5553I |
| Width (mm) | 12 | 12 |
| Length (mm) | 12 | 12 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | ADS5553IPFP | ADS5553IPFPR |
|---|---|---|
| # Input Channels | 2 | 2 |
| Analog Input BW, MHz | 750 | |
| Analog Input BW(MHz) | 750 | |
| Approx. Price (US$) | 37.50 | 1ku | |
| Architecture | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 0.6 | |
| DNL(Max)(+/-LSB) | 0.6 | |
| DNL(Typ), +/-LSB | 0.6 | |
| ENOB, Bits | 11.9 | |
| ENOB(Bits) | 11.9 | |
| INL(Max), +/-LSB | 2.5 | |
| INL(Max)(+/-LSB) | 2.5 | |
| INL(Typ), +/-LSB | 2.5 | |
| Input Buffer | No | |
| Input Range | 2.3 | 2.3V (p-p) |
| Interface | Parallel CMOS | Parallel CMOS Serial SPI Interface |
| Operating Temperature Range, C | -40 to 85 | |
| Operating Temperature Range(C) | -40 to 85 | |
| Package Group | HTQFP | HTQFP |
| Package Size(mm2=WxL) | 80HTQFP: 196 mm2: 14 x 14 | |
| Package Size: mm2:W x L, PKG | 80HTQFP: 196 mm2: 14 x 14(HTQFP) | |
| Power Consumption(Typ), mW | 725 | |
| Power Consumption(Typ)(mW) | 725 | |
| Rating | Catalog | Catalog |
| Reference Mode | Ext,Int | Int Ext |
| Resolution, Bits | 14 | |
| Resolution(Bits) | 14 | |
| SFDR, dB | 84 | |
| SFDR(dB) | 84 | |
| SINAD, dB | 73.4 | |
| SINAD(dB) | 73.4 | |
| SNR, dB | 74 | |
| SNR(dB) | 74 | |
| Sample Rate (max)(SPS) | 65MSPS | |
| Sample Rate(Max), MSPS | 65 |
Eco Plan
| ADS5553IPFP | ADS5553IPFPR | |
|---|---|---|
| RoHS | Compliant | Compliant |
| Pb Free | Yes |
Application Notes
- Clocking High-Speed Data ConvertersPDF, 310 Kb, File published: Jan 18, 2005
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, File published: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
Model Line
Series: ADS5553 (2)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
